Memory system and method using ECC with flag bit to identify modified data

A method of refreshing memory cells in a semiconductor device, the semiconductor device having stored therein an error checking and correction (“ECC”) syndrome and a respective flag bit for each of a plurality of groups of data bits stored in the memory cells, the method comprising:

• in a normal refresh mode, refreshing the memory cells at a rate that is sufficiently high to substantially preclude data retention errors;
• in a reduced power refresh mode, refreshing the memory cells at a rate that is sufficiently low to allow the occurrence of a number of data retention errors that can be corrected by the ECC syndrome;
• and
• in the reduced power refresh mode:
• retrieving the flag bit for the respective group of data stored in the memory cells being refreshed;
• and
• determining if the flag bit has a value indicative of data modification during a period between successive refreshes.

A memory device, comprising:

• memory cells;
• an address decoder, the address decoder being operable to activate cells of the memory cells responsive to received addresses;
• a read data path operable to couple read data from selected memory cells to a plurality of data bus terminals;
• a write data path operable to couple write data from the plurality of data bus terminals to selected memory cells;
• control logic operable to cause the write data to be coupled from the data bus terminals to the memory cells and to cause the read data to be coupled from the memory cells to the data bus terminals;
• refresh circuitry operable to refresh the memory cells in the array at a first rate in a reduced power refresh mode, the refresh circuitry further being operable to refresh the memory cells in the array at a second rate that is significantly faster than the first rate in a normal refresh mode;
• an ECC generator/checker operable in the reduced power refresh mode to generate an error checking and correction (“ECC”) syndrome corresponding to each of a plurality of items of data stored in the memory device;
• and
• an ECC controller operable in the reduced power refresh mode to store respective ECC syndromes generated by the an ECC generator/checker, the ECC controller further being operable to store a flag bit, the ECC controller further being operable when memory cells are refreshed to use at least one of the flag bits to determine if any portion of the respective item of data stored in the memory cells being refreshed has been modified, and, if so, to cause the ECC generator/checker to generate a new ECC syndrome for the item of data and to store the new ECC syndrome generated by the ECC generator/checker.

A computer system, comprising:

• a processor;
• a memory device, comprising:
• memory cells;
• an address decoder, the address decoder being operable to activate memory cells corresponding to received addresses;
• a read data path operable to couple read data from selected memory cells to a plurality of data bus terminals;
• a write data path operable to couple write data from the plurality of data bus terminals to selected memory cells;
• control logic operable to cause the write data to be coupled from the data bus terminals to the memory cells and to cause the read data to be coupled from the memory cells to the data bus terminals;
• refresh circuitry operable to refresh the memory cells at a first rate in a reduced power refresh mode, the refresh circuitry further being operable to refresh the memory cells in the array at a second rate that is significantly faster than the first rate in a normal refresh mode;
• an ECC generator/checker operable in the reduced power refresh mode to generate an error checking and correction (“ECC”) syndrome corresponding to each of a plurality of items of data stored in the memory device;
• an ECC controller operable in the reduced power refresh mode to store respective ECC syndromes generated by the an ECC generator/checker, the ECC controller further being operable to store a flag bit, the ECC controller further being operable when memory cells are refreshed to use at least one of the flag bits to determine if any portion of the respective item of data stored in the memory cells being refreshed has been modified, and, if so, to cause the ECC generator/checker to generate a new ECC syndrome for the item of data and to store the new ECC syndrome generated by the ECC generator/checker;
• and
• a memory controller coupled to the processor and to the memory device, the memory controller being operable to cause the memory device to read and write data.