Method and device for checking the integrity of a logic signal, in particular a clock signal
AssigneeSTMicroelectronics S.r.l.
InventorsFrederic Bancel, Nicolas Berard, Philippe Roquelaure
Life of this patent
Estimating the term…
Abstract
A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.
Claims26
A method for detecting an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of a first type of the logic signal, rising or falling, the method comprising:
- providing at least a first control bit and a second control bit and giving an initial value to the first control bit and an initial value to the second control bit;
- at each edge of the first type of the logic signal, inverting a value of the first control bit after a first delay and inverting a value of the second control bit after a second delay inferior to the first delay;
- and
- detecting an acceleration when the control bits do not have at a same time their respective initial values or their respective inverted initial values.
A device for detecting an acceleration of a logic signal, the device comprising:
- at least a first synchronous flip-flop configured to be clocked by the logic signal and adapted to receive a first control bit, and a second synchronous flip-flop clocked by the logic signal and adapted to receive a second control bit, the flip-flops being arranged so that at each edge of a first type of the logic signal, rising or falling, a value of the first control bit inverts after a first delay and a value of the second control bit inverts after a second delay;
- means for loading an initial value of the first control bit into the first flip-flop and an initial value of the second control bit into the second flip-flop;
- and
- means for supplying an error signal representative of the acceleration when the two bits do not have at a same time their respective initial values or their respective inverted initial values.
A synchronous circuit, comprising:
- synchronous modules configured to be clocked by a logic signal carried by a clock tree;
- and
- a detection device adapted to detect a timing variation in the logic signal, said timing variation representing a time interval less than a longest propagation time of a datum inside at least one of said synchronous modules, said detection device including:
- at least a first flip-flop configured to be clocked by the logic signal and adapted to receive a first control bit;
- a second flip-flop configured to be clocked by the logic signal and adapted to receive a second control bit, the first and second flip-flops being arranged so that at each edge of the logic signal, a value of the first control bit inverts after a first delay and a value of the second control bit inverts after a second delay;
- a first circuit block coupled to the first flip-flop and adapted to load an initial value of the first control bit into the first flip-flop, and coupled to the second flip-flop and adapted to load an initial value of the second control bit into the second flip-flop;
- and
- a second circuit block coupled to the first and second flip-flops and adapted to supply an error signal representative of the timing variation if the control bits do not have at a same time their respective initial values or their respective inverted initial values.
Dependencies are inferred from the claim text.