Design-for-test technique to reduce test volume including a clock gate controller
AssigneeLSI Corporation
InventorNarendra B. Devta-Prasanna
Life of this patent
Estimating the term…
Abstract
Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell.
Claims20
An integrated circuit, comprising:
- a clock gate configured to apply a clock signal to at least a first scan chain of said integrated circuit;
- combinational logic coupled to an input of said clock gate;
- and
- Design-for-Test logic located external to said combinational logic and coupled to said clock gate and a first cell of a second scan chain of said integrated circuit, said Design-for-Test logic configured to control operation of said clock gate based on a logic value of said first cell.
A method of testing an integrated circuit having a clock gate, comprising:
- applying a scan enable signal to Design-for-Test logic of said integrated circuit to enable said clock gate to provide a scan clock signal, wherein said Design-for-Test logic is coupled to said clock gate and a cell of a scan chain of said integrated circuit and is outside of a functional path of said integrated circuit;
- shifting, during application of said scan clock signal, a test pattern to said integrated circuit;
- applying a scan mode signal to said Design-for-Test logic and a logic value to said cell to enable said clock gate to provide a capture clock signal;
- and
- capturing, during application of said capture clock signal, an output pattern from said integrated circuit that is based on said test pattern.
Clock control circuitry for an integrated circuit, comprising:
- clock gate logic configured to provide a gated clock signal;
- and
- Design-for-Test logic coupled to said clock gate logic and configured to control operation of said clock gate logic based on inputs of a scan enable signal, a scan mode signal and a logic value of a scan chain cell of said integrated circuit that is coupled to said Design-for-Test logic.
A library of standard logic elements, comprising:
- a single library element of clock control circuitry having clock gate logic and Design-for-Test logic, said clock gate logic configured to provide a gated clock signal and said Design-for-Test logic configured to control operation of said clock gate logic based on inputs of a scan enable signal, a scan mode signal and a logic value of a scan chain cell of said integrated circuit coupled to said Design-for-Test logic.
Dependencies are inferred from the claim text.