Self-adjusting critical path timing of multi-core VLSI chip
AssigneeInternational Business Machines Corporation
InventorsPeilin Song, Franco Stellari
Life of this patent
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Abstract
A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response signature for each of the reference core and the target core. The response signature of the reference core is compared with the response signature of the target core. A local clock buffer of the target core is adjusted until the response signature of the target core matches the response signature of the reference core.
Claims24
A method for adjusting critical path timing of one or more cores within a multi-core integrated circuit, comprising:
- selecting a reference core and a target core from among a plurality of cores of an integrated circuit;
- using self-test circuitry of the integrated circuit to generate a response signature for each of the reference core and the target core;
- comparing the response signature of the reference core with the response signature of the target core;
- and
- adjusting a local clock buffer of the target core until the response signature of the target core matches the response signature of the reference core, thereby adjusting the critical path timing of the target core.
A multi-core integrated circuit, comprising:
- a first integrated circuit core comprising a first multiple input shift register for generating a first response signature in response to a test pattern processed by the first integrated circuit core;
- a second integrated circuit core comprising a second multiple input shift register for generating a second response signature in response to the test pattern processed by the second integrated circuit core;
- a first latch receiving the first response signature and a scan clock signal;
- a second latch receiving the second response signature and the scan clock signal;
- and
- a checker receiving output from the first and second latches for checking when the first response signature is substantially identical to the second response signature.
An integrated circuit system, comprising:
- a first integrated circuit core comprising a first multiple input shift register for generating a first response signature in response to a test pattern processed by the first integrated circuit core;
- a second integrated circuit core comprising a second multiple input shift register for generating a second response signature in response to the test pattern processed by the second integrated circuit core;
- and
- a checker receiving the first response signature and the second response signature and producing an output signal indicating whether the first response signature is substantially identical to the second response signature.
Dependencies are inferred from the claim text.