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US 8,412,989 B2Granted
Tap time division multiplexing with scan test
AssigneeSTMicroelectronics S.r.l.
InventorRobert Warren
Life of this patent
Estimating the term…
Abstract
An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.
Claims20
An integrated circuit, comprising:
- a plurality of portions, each portion including test control circuitry;
- and
- at least one test input configured to receive test signals,
- wherein the circuit is configured to selectively operate in a test mode in which one or more of the plurality of portions are testable and in a reset mode which has priority over the test mode, and wherein the integrated circuit is configured to selectively switch, based at least in part on the test signals, between operation in the test mode and one of a plurality of other modes including at least one reset mode.
1 more element
A method of testing an integrated circuit including a plurality of portions, each portion including test control circuitry, and at least one test input configured to receive test signals, the method comprising:
- selectively operating the circuit in either a test mode in which one or more of the plurality of portions is testable or a reset mode which has priority over the test mode;
- and
- selectively switching the integrated circuit, based at least in part on the test signals, between operation in the test mode and one of a plurality of other modes including at least one reset mode.
Dependencies are inferred from the claim text.