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US 8,412,981 B2Granted
Core sparing on multi-core platforms
AssigneeIntel Corporation
InventorsAlberto J. Munoz, Sorin Iacobovici
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Abstract
Methods and apparatus to provide core sparing on multi-core platforms are described. In an embodiment, stored core state information of a target core (e.g., a core that has detected a fault condition (e.g., within its circuitry) or a request to offload operations from the target core (e.g., to enable run-time diagnostics without interfering with system software)) may be read by a spare core which is to operationally replace the target core. Other embodiments are also described.
Claims34
A processor comprising:
- first logic circuitry to cause architectural state information of a first processor core to be stored to a shadow memory in response to an occurrence of a core sparing event;
- second logic circuitry to cause error logging state information of said first processor core to be stored to said shadow memory;
- and,
- third logic circuitry to select a second processor core to read at least the stored architectural state information in response to the occurrence of the core sparing event.
1 more element
A method, comprising:
- storing error logging state information of a first processor core into a machine specific register of said first processor core;
- detecting an occurrence of a core sparing event concerning said first processor core;
- storing architectural state of said first processor core in a shadow memory in response to the occurrence of the core sparing event;
- storing said error logging state information of said first processor core into said shadow memory;
- and
- selecting a second processor core as a spare core to replace the first processor core.
3 more elements
A computing system comprising:
- a plurality of processor cores of a processor
- a memory to store a plurality of instructions;
- the processor to fetch the instructions from the memory and execute them to operationally replace a first processor core of the plurality of processor cores with a second processor core of the plurality of processor cores, where, the first processor core comprises:
- first logic circuitry to cause architectural state information of the first processor core to be stored to a shadow memory in response to an occurrence of a core sparing event;
- second logic circuitry to cause error logging state information of said first processor core to be stored to said shadow memory;
- and,
- third logic circuitry to select a second processor core to read at least the stored architectural state information in response to the occurrence of the core sparing event.
4 more elements
Dependencies are inferred from the claim text.