Data negotiation using serial voltage identification communication

A method, comprising:

• initiating communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators;
• determining a first speed associated with a first voltage regulator of the plurality of voltage regulators that is slower than a second voltage regulator of the plurality of voltage regulators, wherein the plurality of voltage regulators is electrically coupled to the integrated circuit;
• transmitting address information to the plurality of voltage regulators that are electrically coupled to the integrated circuit at the first speed;
• determining a second speed associated with a voltage regulator to which the address information is associated, comprising:
• initializing a counter;
• driving a next bit after an address field of a protocol packet to a first state,
• monitoring an alert interconnect to determine a number of clock cycles associated with both the CPU driving the next bit to a second state and a number of clock cycles associated with the voltage regulator to which to which the address information is associated driving the next bit to the second state;
• and
• communicating at the second speed to the voltage regulator to which the address information is associated.

An apparatus comprising:

• an integrated circuit comprising:
• circuitry to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators, comprising:
• initializing a counter, and
• driving a first bit of a protocol packet to zero;
• circuitry to determine a first speed associated with a first voltage regulator of the plurality of voltage regulators that is slower than a second voltage regulator of the plurality of voltage regulators, wherein the plurality of voltage regulators is electrically coupled to the integrated circuit, comprising:
• monitoring an interconnect to determine a maximum number of clock cycles associated with the plurality of voltage regulators to drive the first bit of the protocol packet to a second state;
• circuitry to transmit address information to the plurality of voltage regulators that are electrically coupled to the integrated circuit at the first speed;
• circuitry to determine a second speed associated with a voltage regulator to which the address information is associated;
• and
• circuitry to communicate at the second speed to the voltage regulator to which the address information is associated.

An apparatus, comprising:

• an integrated circuit comprising:
• circuitry to initiate communication at an integrated circuit that is electrically coupled to a plurality of voltage regulators;
• circuitry to determine a first speed associated with a first voltage regulator of the plurality of voltage regulators that is slower than a second voltage regulator of the plurality of voltage regulators, wherein the plurality of voltage regulators is electrically coupled to the integrated circuit;
• circuitry to transmit address information to the plurality of voltage regulators that are electrically coupled to the integrated circuit at the first speed;
• circuitry to determine a second speed associated with a voltage regulator to which the address information is associated, comprising:
• initializing a counter;
• driving a next bit after an address field of a protocol packet to a first state;
• monitoring an alert interconnect to determine a number of clock cycles associated with both the CPU driving the next bit to a second state and a number of clock cycles associated with the voltage regulator to which to which the address information is associated driving the next bit to the second state;
• and
• circuitry to communicate at the second speed to the voltage regulator to which the address information is associated.

A system comprising:

• a plurality of voltage regulators;
• an interconnect that is electrically coupled to an integrated circuit and the plurality of voltage regulators;
• and
• the integrated circuit comprising:
• circuitry to initiate communication at an integrated circuit that is electrically coupled to the plurality of voltage regulators, comprising:
• initializing a counter, and
• driving a first bit of a protocol packet to a first state;
• circuitry to determine a first speed associated with a first voltage regulator of the plurality of voltage regulators that is slower than a second voltage regulator of the plurality of voltage regulators, wherein the plurality of voltage regulators is electrically coupled to the integrated circuit, comprising
• monitoring an interconnect to determine a maximum number of clock cycles associated with the plurality of voltage regulators to drive the first bit of the protocol packet to a second state;
• circuitry to transmit address information to the plurality of voltage regulators that are electrically coupled to the integrated circuit at the first speed;
• circuitry to determine a second speed associated with a voltage regulator to which the address information is associated;
• and
• circuitry to communicate at the second speed to the voltage regulator to which the address information is associated.

A system, comprising:

• a plurality of voltage regulators;
• an interconnect that is electrically coupled to an integrated circuit and the plurality of voltage regulators;
• and
• the integrated circuit comprising:
• circuitry to initiate communication at an integrated circuit that is electrically coupled to the plurality of voltage regulators;
• circuitry to determine a first speed associated with a first voltage regulator of the plurality of voltage regulators that is slower than a second voltage regulator of the plurality of voltage regulators, wherein the plurality of voltage regulators is electrically coupled to the integrated circuit;
• circuitry to transmit address information to the plurality of voltage regulators that are electrically coupled to the integrated circuit at the first speed;
• circuitry to determine a second speed associated with a voltage regulator to which the address information is associated, comprising:
• initializing a counter,
• driving a next bit after an address field of a protocol packet to the first state, and
• monitoring an alert interconnect to determine a number of clock cycles associated with both the CPU driving the next bit to a second state and a number of clock cycles associated with the voltage regulator to which to which the address information is associated driving the next bit to the second state;
• and
• circuitry to communicate at the second speed to the voltage regulator to which the address information is associated.