Global synchronization of parallel processors using clock pulse width modulation

An apparatus for synchronizing a plurality of processors in a parallel computing system, the apparatus comprising:

• a hardware module for generating a clock signal and for performing a pulse width modification on the clock signal, the pulse width modification changing a pulse width within a clock period in third clock signal;
• a clock splitter for distributing the pulse width modified clock signal to a plurality of processors in the parallel computing system to synchronize the processors;
• one or more detection circuit, associated with the processors, for receiving the pulse width modified clock signal;
• a plurality of flip flops, in the one or more detection circuit, for oversampling the pulse width modified clock signal;
• a hardware logic gate, in the one or more detection circuit, for generating a synchronization signal based on the oversampling, the generated synchronization signal used to synchronize the processors.

A computer program product for synchronizing a plurality of processors in a parallel computing system, the computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions run by the processing circuit for performing steps of:

• generating a clock signal;
• performing a pulse width modification on the clock signal, the pulse width modification changing a pulse width within a clock period in the clock signal;
• distributing the pulse width modified clock signal to a plurality of processors in the parallel computing system to synchronize the processors;
• receiving, at one or more detection circuit associated with the processors, the distributed pulse width modified clock signal;
• oversampling the received pulse width modified clock signal;
• and
• generating a synchronization signal based on the oversampling, the generated synchronization signal used to synchronize the processors.