Method and apparatus for cache control

A processor comprising:

• a power management unit configured:
• change the operating point of the processor from a first operating point to a second operating point;
• read a committed instructions per second (CIPS) value;
• calculate a sum of a threshold value and a guard band value;
• compare the CIPS value to the threshold value and the sum;
• selectively alter power of a first subset of a plurality of ways of a cache memory responsive to changing to the second operating point if the CIPS value is less than the threshold value;
• power on all ways of the cache memory if the CIPS value is greater than the sum;
• wherein no additional ways of the cache memory are powered on or off if the CIPS value is greater than the threshold value and less than the sum;
• and
• wherein the at least one execution unit of the processor is configured to, subsequent to selectively altering power of the first subset of the plurality of ways, access one or more ways of a second subset of the plurality of ways from which power was altered.

A method comprising:

• calculating a first threshold value and a second threshold value, wherein the second threshold value is a sum of the first threshold value and a guard band value;
• comparing a workload indicator value to first the threshold value and the second threshold value, wherein the workload indicator value is a committed instructions per second (CIPS) value indicative of a number of instructions for which corresponding results are committed to registers each second;
• selectively removing power from a subset of a plurality of ways of a cache memory if a workload indicator value of a processor is less than a first threshold value;
• and
• powering on any previously powered down ways of the cache memory if the workload indicator value is greater than a second threshold;
• wherein power to ways of the cache memory is altered if the workload indicator value is greater than the first threshold value and less than the second threshold.

A method comprising:

• changing a performance state of a processor from a first performance state to a second performance state, wherein the first performance state comprises operating a core of the processor at a first voltage and a first clock frequency, and wherein the second performance state comprises operating the core at a second voltage less than the first voltage and a second clock frequency less than the first clock frequency;
• reading a committed instructions per second (CIPS) value;
• calculating a sum of a threshold value and a guard band value;
• comparing the CIPS value to the threshold value and the sum;
• selectively removing power from one or more ways of a cache memory responsive to changing to the second performance state if the CIPS value is less than the threshold value;
• powering on all ways of the cache memory if the CIPS value is greater than the sum,
• wherein no additional ways of the cache memory are powered on or off if the CIPS value is greater than the threshold value and less than the sum;
• and
• processing one or more instructions in the core of the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes the core accessing one or more ways of the cache memory from which power was not removed.

A computer readable medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including:

• a power management unit configured to
• change the operating point of a processor from a first operating point to a second operating point;
• read a committed instructions per second (CIPS) value;
• calculate a sum of a threshold value and a guard band value;
• compare the CIPS value to the threshold value and the sum;
• selectively alter power of a first subset of a plurality of ways of a cache memory responsive to changing to the second operating point if the CIPS value is less than the threshold value;
• power on all ways of the cache memory if the CIPS value is greater than the sum;
• wherein no additional ways of the cache memory are powered on or off if the CIPS value is greater than the threshold value and less than the sum;
• and
• wherein the at least one execution unit is configured to, subsequent to selectively altering power of the first subset of the plurality of ways, access one or more ways of a second subset of the plurality of ways from which power was altered.