Circuit, system and method for selectively turning off internal clock drivers
AssigneeMosaid Technologies Incorporated
InventorGeorge B. Raad
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Abstract
The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.
Claims15
Clock control circuitry, comprising:
- command detection circuitry configured to generate a gating signal based on a command signal input having first possible signal states, where the command signal input is concurrent with an absence of a read/write burst operation, the gating signal;
- i) indicating idle time in a memory device when the command signal input to the memory device has the first possible signal states at one time, and ii) indicating otherwise when the command signal input has remaining possible signal states;
- and
- clock gating circuitry coupled to said command detection circuitry for receiving a system clock and for selectively gating said system clock in response to said gating signal.
A memory device, comprising:
- a memory array;
- and
- clock control circuitry in communication with said memory array and for receiving a system clock, said clock control circuitry comprising:
- command detection circuitry configured to generate a gating signal based on a command signal input having first possible signal states, where the command signal input is concurrent with an absence of a read/write burst operation, the gating signal indicating idle time in a memory device when the command signal i) input to the memory device has the first possible signal states at one time, and ii) indicating otherwise when the command signal input has remaining possible signal states;
- and
- clock gating circuitry coupled to said command detection circuitry for receiving said system clock and for selectively gating said system clock in response to said gating signal.
Dependencies are inferred from the claim text.