Method of enhancing power saving in an integrated electronic system with distinctly powered islands of functional circuitries and related device architecture

A method of power saving in an integrated circuit device including an analog circuit receiving an external reference frequency signal, and at least one internal clock generating circuit configured to receive a root clock signal from the analog circuit, the integrated circuit device comprising differently powered islands of functional circuits commanded by an external controller, the method comprising:

• defining an off-switchable analog circuit island including the at least one internal clock generating circuit;
• at power-on of the integrated circuit device, supplying to clocked digital circuits of the integrated circuit device an auxiliary clock signal from the external controller, the auxiliary clock signal having a frequency lower than the root clock signal;
• supplying external reset commands to the integrated circuit device until reaching an active functioning condition of the integrated circuit device;
• and
• interrupting the auxiliary clock signal and enabling supply of the root clock signal to the clocked digital circuits when the active functioning condition of the integrated circuit device is reached.

An integrated circuit device configured to communicate with an external controller generating an auxiliary clock signal and external asynchronous reset commands, the integrated circuit device comprising:

• an analog circuit configured to receive an external reference frequency signal;
• at least one internal clock generating circuit configured to receive a root clock signal from said analog circuit;
• a digital interface circuit;
• and
• differently powered islands of functional circuits configured to be commanded by the external controller coupled to said digital interface circuit;
• said differently powered islands including
• a first digital circuit island including an interface and wake-up logic circuit, a state machine configured to trace a plurality of power saving states, and at least one system register configured to have content be retained through sleep functioning condition intervals,
• a second off-switchable digital circuit island including digital circuits that can be switched off when the integrated circuit device enters a sleep mode, and
• a third off-switchable analog circuit island, the auxiliary clock signal and the external asynchronous reset commands being supplied to the clocked digital circuits of the first digital circuit island and of the second off-switchable digital circuit island.