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US 8,412,965 B2Granted
PWM timer for power supply
AssigneeSTMicroelectronics S.r.l.
InventorThomas L. Hopkins
Life of this patent
Estimating the term…
Abstract
A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.
Claims20
A circuit, comprising:
- a control circuit configured to generate a first control signal for application to a first control terminal and generate a second control signal for application to a second control terminal, the control circuit comprising:
- a first delay timer configured to be triggered by a first event signal to count and cause a state change of the first control signal;
- a second delay timer configured to be triggered by a second event signal to count and cause an opposite state change of the first control signal;
- a third delay timer configured to be triggered by a third event signal to count and cause a state change of the second control signal;
- and
- a fourth delay timer configured to be triggered by a fourth event signal to count and cause an opposite state change of the second control signal.
3 more elements
A circuit, comprising:
- a control circuit configured to generate a first control signal for application to a first control terminal and generate a second control signal for application to a second control terminal, the control circuit comprising:
- a first circuit configured to be triggered by a first event signal to delay a state change of the first control signal for a first delay time written to a first register;
- a second circuit configured to be triggered by a second event signal to delay an opposite state change of the first control signal for a second delay time written to a second register;
- a third circuit configured to be triggered by a third event signal to delay a state change of the second control signal for a third delay time written to a third register;
- and
- a fourth circuit configured to be triggered by a fourth event signal to delay an opposite state change of the second control signal for a fourth delay time written to a fourth register.
3 more elements
A circuit, comprising:
- a control circuit configured to generate a first control signal for application to a first control terminal and generate a second control signal for application to a second control terminal, the control circuit comprising:
- a first counter triggered by a first event signal;
- a second counter triggered by a second event signal;
- a first circuit configured to cause a state change of the first control signal in response to a first count of the first counter;
- a second circuit configured to cause an opposite state change of the first control signal in response to a first count of the second counter;
- a third circuit configured to cause a state change of the second control signal in response to a second count of the first counter;
- and
- a fourth circuit configured to cause an opposite state change of the second control signal in response to a second count of the second counter.
5 more elements
Dependencies are inferred from the claim text.