Data exchange and communication between execution units in a parallel processor

An integrated-circuit processing device operable to execute operations in parallel, the integrated-circuit processing device comprising:

• an instruction sequencing hardware circuit operable to receive an instruction configured to facilitate data transfer among execution lanes;
• an inter-lane switch coupled to the execution lanes and operable to establish a data-transfer path to enable data to be transferred among the execution lanes;
• potential source lanes among the execution lanes, the potential source lanes operable to generate data-transfer requests;
• a control circuit configured to:
• examine, in response to the instruction, the data-transfer requests;
• determine, from among the potential source lanes, source lanes operable to send data to requested destination lanes among the execution lanes;
• provide confirmation information to the potential source lanes, the confirmation information indicating whether the potential source lanes may send data to the requested destination lanes during a data-transfer interval;
• and
• output source lane identifiers to the requested destination lanes, a source lane identifier including identification information to identify a source lane from which to receive data during the data-transfer interval;
• and
• an associated multiplexing circuit operable to form, for each of the requested destination lanes, a data-transfer path between (i) one of a plurality of communication lanes within the inter-lane switch identified by a corresponding one of the source lane identifiers and (ii) one or more of the requested destination lanes.

A non-transitory computer-readable medium storing instructions that are configured to be executed by a computing device to cause the computing device to generate mask information corresponding to an integrated circuit, the instructions comprising:

• instructions for generating an instruction sequencing circuit operable to receive an instruction configured to facilitate data transfer among execution lanes;
• instructions for generating an inter-lane switch coupled to the execution lanes and operable to establish a data-transfer path to enable data to be transferred among the execution lanes;
• instructions for generating potential source lanes among the execution lanes, the potential source lanes operable to generate data-transfer requests;
• instructions for generating a control circuit configured to:
• examine, in response to the instruction, the data-transfer requests;
• determine, from among the potential source lanes, source lanes operable to send data to requested destination lanes among the execution lanes;
• provide confirmation information to the potential source lanes, the confirmation information indicating whether the potential source lanes may send data to the requested destination lanes during a data-transfer interval;
• and
• output source lane identifiers to the requested destination lanes, a source lane identifier including identification information to identify a source lane from which to receive data during the data-transfer interval;
• and
• instructions for forming, for each of the requested destination lanes, via an associated multiplexing circuit, the data-transfer path between (i) one of a plurality of communication lanes within the inter-lane switch identified by a corresponding one of the source lane identifiers and (ii) one or more of the requested destination lanes.

A non-transitory computer-readable medium having instructions stored thereon, the instructions comprising:

• instructions for receiving data-transfer requests from associated potential source lanes among execution lanes;
• instructions for determining, from among the potential source lanes, source lanes operable to send data to requested destination lanes among the execution lanes;
• instructions for providing confirmation information to the potential source lanes, the confirmation information indicating whether the potential source lanes may send data to the requested destination lanes during a data-transfer interval;
• instructions for outputting source lane identifiers to the requested destination lanes, a source lane identifier including identification information to identify a source lane from which to receive data during the data-transfer interval;
• and
• instructions for forming, for each of the requested destination lanes, via an associated multiplexing circuit, a data-transfer path between (i) one of a plurality of communication lanes within an inter-lane switch identified by a corresponding one of the source lane identifiers and (ii) one or more of the requested destination lanes.