US 8,412,902 B2 · Signal processor and signal processing system

Abstract

In a signal processor including storage sections, a start address for starting output of data from an external memory, is input from an external controller to the start address input section. The signal output section outputs a start signal based on a download start instruction from the external controller, and outputs an end signal when download is completed. The output instruction section outputs, based on the start signal, to the external memory a data output instruction of download data for a designated storage section, starting from the start address, and stops output of the data output instruction based on the end signal. The write instruction section outputs a write instruction to the storage sections that allows data writing only to the designated storage section, and the download data is written to the designated storage section when the start signal is input to the output instruction section.

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Claims6

Dependent claims

A signal processor comprising:

a plurality of storage sections;
a start address input section to which a start address is input from an external controller, the start address indicating an address for starting output of data from an external memory that stores a set of data to be downloaded to the plurality of storage sections;
a signal output section adapted to output a start signal based on a download start instruction input from the external controller, and to output an end signal when download has been completed of data to be downloaded to at least one storage section designated by the external controller;
an output instruction section that:
(A) when the start signal is input thereto, is adapted to output to the external memory a data output instruction to output data corresponding to bytes of the data to be downloaded to the at least one designated storage section, starting from the start address, and (B) when the end signal is input thereto, is adapted to stop output of the data output instruction;
and
a write instruction section that is adapted to receive input of the at least one designated storage section from the external controller, and, based upon the input, output a write instruction to the plurality of storage sections which prohibits writing of data to the plurality of storage sections other than the at least one designated storage section, and causes the data to be downloaded to be written only to the at least one designated storage section when the start signal is input to the output instruction section.

4 more elements

A signal processing system comprising:

a signal processor comprising:
(a) a plurality of storage sections,
(b) a start address input section to which a start address is input from an controller, the start address indicating an address for starting output of data from a memory that stores a set of data to be downloaded to the plurality of storage sections,
(c) a signal output section adapted to output a start signal based on a download start instruction input from the controller, and to output an end signal when download has been completed of data to be downloaded to at least one storage section designated by the controller,
(d) an output instruction section that:
(A) when the start signal is input thereto, is adapted to output to the memory a data output instruction to output data corresponding to bytes of the data to be downloaded to the at least one designated storage section, starting from the start address, and (B) when the end signal is input thereto, is adapted to stop output of the data output instruction, and
(e) a write instruction section that is adapted to receive input of the at least one designated storage section from the external controller;
and, based upon the input, output a write instruction to the plurality of storage sections which prohibits writing of data to the plurality of storage sections other than the at least one designated storage section, and causes the data to be downloaded to be written only to the at least one designated storage section when the start signal is input to the output instruction section;
the memory that stores the act of data to be downloaded to the plurality of storage sections;
and,
the controller adapted to output the start address that indicates where to start output of data stored in the memory, a designation of at least one storage section that is a download destination of the data, and a download start instruction;
wherein the signal processor is adapted to write the data stored in the memory to the at least one designated storage section, based on the start address, the designation of the at least one storage section, and the download start Instruction, which are output by the controller.

9 more elements

Dependencies are inferred from the claim text.

Description7,764 words

Summary1,337 words

#This application is based on and claims priority under 35 U.S.C. §119 from Japanese Patent Application No. 2008-330412 filed on Dec. 25, 2008, the disclosure of which is incorporated by reference herein.

#1. Field of the Disclosure

#The disclosure relates to a signal processor that performs signal processing based on data downloaded automatically from a memory, and to a signal processing system of the same.

Brief description of the drawings12 figures

#Exemplary embodiments of the present disclosure will be described in detail based on the following figures, wherein:

#FIG. 1 is a functional block diagram showing an example of a schematic configuration of a signal processing system according to a first exemplary embodiment;

#FIG. 2 is a flow chart showing an example of signal processing executed in an external CPU according to the first exemplary embodiment;

Detailed description6,112 words

#The exemplary embodiments of the present disclosure are described and illustrated below to encompass a signal processor that performs signal processing based on data downloaded automatically from a memory, and to a signal processing system of the same. Of course, it will be apparent to those of ordinary skill in the art that the preferred embodiments discussed below are exemplary in nature and may be reconfigured without departing from the scope and spirit of the present disclosure. However, for clarity and precision, the exemplary embodiments as discussed below may include optional steps, methods, and features that one of ordinary skill should recognize as not being a requisite to fall within the scope of the present disclosure. Hereinafter, an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

#A detailed explanation will now be given of a signal processing system of the first exemplary embodiment. FIG. 1 is a functional block diagram showing an example of a schematic configuration of a signal processing system of the first exemplary embodiment. A signal processor 16 of the present exemplary embodiment is an example of a signal processor that performs processing of image signals, sound signals, or the like in a hardwired processing section 38.

#A signal processing system 10 of the exemplary embodiment includes an external CPU 12, an external memory 14, and the signal processor (LSI) 16.

Facts

Application

12/645,001Filed 22 Dec 2009

Priority

JP 2008-33041225 Dec 2008

Published

US 2010/0169600 A11 Jul 2010

Granted

2 Apr 2013

Term ends

2 Jan 2031

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 376 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification2 codes

G06F 12/1441
The protection being physical, e.g. cell, word, block: for a range
G06F
Computing and data processing

Timeline

25 Dec 2008Priority claimedJP 2008-330412
22 Dec 2009Application filedUS 12/645,001
6 Jan 2010Assigned to Oki Semiconductor Co., Ltd.assignment of assignor's interest
1 Jul 2010PublishedUS 2010/0169600 A1
2 Apr 2013GrantedUS 8,412,902 B2
21 Mar 2014Assigned to Lapis Semiconductor Co., Ltd.change of name
12 Oct 2026TodayWithin its term
2 Jan 2031Term endsEstimated, includes 376 days of adjustment

Signal processor and signal processing system

Life of this patent

Signal processor and signal processing system

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims6

Description7,764 words

Drawings

Classification2 codes

Life of this patent

Description7,764 words