Low-level conditional synchronization support
AssigneeMicrosoft Corporation
InventorsDavid Harper, Burton Smith
Life of this patent
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Abstract
A low-overhead conditional synchronization instruction operates on a synchronization variable which includes a lock bit, a state specification, and bits for user-defined data. The instruction specifies the memory address of the synchronization variable and a condition. During the synchronization instruction the condition is compared to the state specification within an atomic region. The match succeeds if the condition matches the state specification and the lock bit is clear. The synchronization instruction may operate with a cache under a cache coherency protocol, or without a cache, and may include a timeout operand.
Claims20
A synchronization method utilizing a lock bit in a computing system which also has a cache, the cache having cache lines, operation of the cache in the computing system being subject to a cache protocol which has at least a shared state and an exclusive state, the method comprising the steps of:
- acquiring a cache line in the shared state outside an atomic region;
- comparing a condition to a state specification outside the atomic region, the state specification occupying a different location in the computing system than the lock bit occupies in the computing system, and the state specification capable of identifying at least three states;
- if match requirements are met in the shared state then entering the atomic region and acquiring the cache line in the exclusive state, comparing the condition to the state specification within the atomic region and if the match requirements are met then setting the lock bit within the atomic region and returning a success indicator, and if the match requirements are not met within the atomic region then exiting the atomic region without setting the lock bit, the match requirements being met when the condition matches the state specification and the lock bit is clear;
- and
- if the match requirements are not met in the shared state then returning a failure indicator.
A computer system comprising:
- a memory having a lock bit stored at a memory location and a state specification stored in at least two other bits which are also located at the memory location;
- a processor in operable communication with the memory;
- a cache configured to operate under a cache protocol having a shared state and an exclusive state;
- and
- an indicator generated by the following method:
- acquiring a cache line in the shared state outside an atomic region;
- comparing a condition to the state specification outside the atomic region;
- if match requirements are met in the shared state then entering the atomic region and acquiring the cache line in the exclusive state, comparing the condition to the state specification within the atomic region and if the match requirements are met then setting the lock bit within the atomic region and returning a success indicator, the match requirements being met when the condition matches the state specification and the lock bit is clear, and if the match requirements are not met within the atomic region then exiting the atomic region without setting the lock bit;
- and
- if the match requirements are not met in the shared state then returning a failure indicator.
A storage medium configured with computer code for controlling a system to perform a synchronization method utilizing a lock bit, the method operating in connection with a cache protocol having a shared state and an exclusive state, the method comprising the steps of:
- acquiring a cache line in the shared state outside an atomic region;
- comparing a condition to a state specification outside the atomic region, the state specification capable of specifying at least three states and being located in different bits than the lock bit;
- if match requirements are met in the shared state then entering the atomic region and acquiring the cache line in the exclusive state, comparing the condition to the state specification within the atomic region and if the match requirements are met then setting the lock bit within the atomic region and returning a success indicator, the match requirements being met when the condition matches the state specification and the lock bit is clear, and if the match requirements are not met within the atomic region then exiting the atomic region without setting the lock bit;
- and
- if the match requirements are not met in the shared state then returning a failure indicator.
Dependencies are inferred from the claim text.