Memory controller and associated control method
AssigneeMStar Semiconductor, Inc.
InventorsYo-Lin Chen, Hsian-Feng Liu, Ming-Chieh Yeh
Life of this patent
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Abstract
A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
Claims16
A memory controller, coupled to a memory module, comprising:
- a command generator that generates a read command and provides the read command to the memory module;
- a first-in-first-out (FIFO) buffer that stores data received from the memory module according to a data strobe signal generated by the memory module in response to receiving the read command;
- a write pointer that generates a write count according to the data strobe signal, the write count being associated with a position of the stored data in the FIFO buffer;
- a read pointer that maintains a read count according to a number of times that data in the FIFO buffer is read, the read count being associated with a position of the read data in the FIFO buffer;
- and
- a pointer calibration unit that sets the write count to be same as the read count after the read command is generated and before the memory module outputs the data.
A method for controlling a memory controller, the memory controller coupled to a memory module, the method comprising:
- providing information of a latency of the memory module;
- generating a read command that is provided to the memory module;
- storing data received from the memory module into a first-in-first-out (FIFO) buffer of the memory controller;
- and
- setting a write count to be same as a read count during the latency of the memory module when the read command is generated, the write count being associated with a position of written data in the FIFO buffer, the read count being associated with a position of read data in the FIFO buffer.
A method for controlling a memory controller, the memory controller coupled to a memory module, the method comprising:
- providing information of a latency of the memory module;
- determining whether a read command is generated by a command generator of the memory controller;
- comparing a read count with a write count when the read command is generated, the write count being associated with a position of written data in a first-in-first-out (FIFO) buffer of the memory controller, the read count being associated with a position of read data in the FIFO buffer;
- and
- setting the write count to be same as the read count during the latency when the write count differs from the read count.
Dependencies are inferred from the claim text.