Hybrid implementation for error correction codes within a non-volatile memory system

A method for storing data within a non-volatile memory, comprised a plurality of blocks in an array formed on a semiconductor substrate, of a memory system, the method comprising:

• identifying one of the plurality of blocks into which the data is to be stored;
• obtaining an indicator associated with the identified block, the indicator having a value indicative of a number of times the first block has been erased;
• determining whether the indicator is less than a threshold value,
• responsive to the indicator being less than the threshold value, encoding the data using the first algorithm and then writing the data encoded using a first error detection algorithm into the identified block;
• responsive to the indicator not being less than the threshold value, encoding the data using a second algorithm and then writing the data encoded using a second error detection algorithm into the identified block, the second error detection algorithm having a higher error detection capability than the first error detection algorithm;
• repeating the identifying, obtaining, determining, encoding, and writing steps for another block in the array;
• wherein, as a result of the repeating step, a first block in the array stores data encoded according to the first algorithm, and a second block in the array stores data encoded according to the second algorithm.

A method for reading data within a non-volatile memory comprised of a plurality of blocks in an array formed on a semiconductor substrate, the method comprising:

• identifying one of the plurality of blocks from which data is to be read;
• obtaining an indicator associated with the identified block, the indicator having a value indicative of a number of times the identified block has been erased;
• determining whether the indicator is less than a threshold value,
• responsive to the indicator being less than the threshold value, decoding the data using a first error detection algorithm;
• responsive to the indicator not being less than the threshold value, decoding the data using a second error detection algorithm, the second error detection algorithm having a higher error detection capability than the first error detection algorithm.

A memory system comprising:

• a non-volatile memory array formed on a semiconductor substrate, the array including a plurality of blocks;
• code devices for identifying a block into which data is to be stored;
• code devices for obtaining an indicator associated with the identified block, the indicator having a value arranged to indicate whether the block is a reclaimed block;
• code devices for encoding the data using a first error detection algorithm responsive to the indicator meeting a criterion, and for encoding the data using a second error detection algorithm responsive to the indicator not meeting the criterion, the second error detection algorithm having a higher error detection capability than the first error detection algorithm;
• code devices for writing encoded data into the identified block;
• and
• a memory area that stores the code devices.

A memory system comprising:

• a non-volatile memory array formed on a semiconductor substrate, the array including a plurality of blocks;
• code devices for identifying a block into which data is to be stored;
• code devices for obtaining an indicator associated with the identified block, the indicator having a value indicative of a number of times the identified block has been erased;
• code devices for determining whether the indicator is less than a threshold value,
• code devices for encoding the data using a first algorithm responsive to—the indicator being less than the threshold value;
• code devices for writing the data encoded using the first algorithm into the identified block;
• code devices for encoding the data using a second algorithm responsive to determining that the data is not to be encoded using the first algorithm, the second error detection algorithm having a higher error detection capability than the first error detection algorithm;
• code devices for writing the data encoded using the second algorithm into the identified block;
• and
• a memory area that stores the code devices.

A memory system comprising:

• a non-volatile memory array formed on a semiconductor substrate, the array including a plurality of blocks, each including data;
• code devices for identifying a block;
• code devices for obtaining an indicator associated with the identified block, the indicator having a value indicative of a number of times the block has been erased;
• code devices for determining whether the indicator is less than a threshold value,
• code devices for decoding the data using a first error detection algorithm responsive to the indicator being less than the threshold value;
• code devices for decoding the data using a second error detection algorithm responsive to the indicator not being less than the threshold value, the second error detection algorithm having a higher error detection capability than the first error detection algorithm;
• and
• a memory area that stores the code devices.