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US 8,412,855 B2Granted
Write combining protocol between processors and chipsets
AssigneeIntel Corporation
InventorsKenneth C. Creta, Aaron T. Spink, Lance E. Hacking, Sridhar Muthrasanallur, Jasmin Ajanovic
Life of this patent
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Abstract
Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.
Claims17
A method comprising:
- receiving a plurality of write transactions from a processor with a controller hub, the plurality of write transactions being identified as write combinable transactions, based on a per memory page attribute, and being destined for a device coupled to the controller hub;
- storing data associated with the plurality of write transactions to a buffer of the controller hub in response to the plurality of write transactions being identified as write combinable transactions;
- determining whether a latency condition exists, the latency condition including at least a delay in receiving a next combinable write transaction from the processor;
- flushing the data associated with the plurality of write transactions as write combined data in a single transaction to the device in response to determining the latency condition exists without receiving a flush signal from the processor;
- sending a write completion signal to the processor for each of the plurality of write transactions in response to the data being flushed to the device, wherein the processor is to refrain from issuing order-dependent transactions between detection of flushing the data and receipt of the write completion signal;
- and
- tagging a plurality of buffers of the controller hub with source identifiers associated with one or more write combinable write transactions to allow for ignoring of flushing signals from a non-associated processor.
4 more elements
An apparatus comprising:
- a hub to be coupled to a processor and a device, the hub comprising:
- receiving logic to receive a plurality of combinable write transactions from the processor, wherein the plurality of combinable write transactions are determined to be combinable based on a per memory page attribute;
- a buffer to store data associated with the plurality of combinable write transactions;
- latency detection logic to detect occurrence of a latency condition, the latency condition including at least a delay in receiving a next combinable write transaction from the processor;
- flushing the data associated with the plurality of combinable write transactions as write combined data in a single transaction to the device in response to the latency detection logic detecting the latency condition without receiving a flush signal from a processor;
- and
- protocol logic to send a write completion signal to the processor for each of the plurality of write transactions in response to the data being flushed to the device, wherein the processor is to refrain from issuing order-dependent transactions between detection of flushing the data and receipt of the write completion signal and wherein a plurality of buffers of the hub are to be tagged with source identifiers associated with one or more write combinable write transactions to allow for ignoring of flushing signals from a non-associated processor.
4 more elements
An apparatus comprising:
- a hub to be coupled to a transmitting device and a receiving device, the hub including:
- a buffer;
- receiving logic to receive a first combinable write transaction and a second combinable write transaction from the transmitting device, wherein the first and second combinable write transactions are determined to be combinable based on a per memory page attribute;
- and
- a write combining module to
- store first data associated with the first combinable write transaction in the buffer and store second data associated with the second combinable write transaction in the buffer,
- flush the first data and the second data as combined data in a single transaction to the receiving device in response to detecting a latency condition and without receiving a flush signal from a processor, the latency condition including at least a delay in receiving a next combinable write transaction from the processor;
- send a first write completion signal corresponding to the first combinable write transaction and a second write completion signal corresponding to the second combinable write transaction after the write combinable module flushes the first data and the second data as combined data in the single transaction to the receiving device, wherein the processor is to refrain from issuing order-dependent transactions between detection of flushing the data and receipt of the write completion signal and wherein a plurality of buffers of the hub are to be tagged with source identifiers associated with one or more write combinable write transactions to allow for ignoring of flushing signals from a non-associated processor.
5 more elements
Dependencies are inferred from the claim text.