Two pin serial bus communication interface
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.
Claims5
An integrated circuit comprising:
- A. functional circuits having inputs and outputs;
- B. data I/O circuitry having one bi-directional data signal lead that is accessible from outside the integrated circuit, a data input lead that is separate from the bi-directional data signal lead and that is coupled to the one bi-directional data signal lead, and a data output lead that is separate from the bi-directional data signal lead and the data input lead, and that is coupled to the one bi-directional data signal lead;
- C. a clock input lead;
- D. data circuitry having an input connected to the data input lead, an output connected to the data output lead, control inputs, outputs connected with the inputs of the functional circuits, and inputs connected with the outputs of the functional circuits;
- E. instruction circuitry having an input connected to the data input lead, control inputs, and a control output;
- F. address circuitry having an input connected to the data input lead, control inputs, and a control output;
- and
- G. port controller circuitry having a clock input connected to the clock input lead, a data input connected to the data input lead, a data control output connected to the control input of the data circuitry, an instruction control output connected to the control input of the instruction circuitry, an instruction control input connected to the control output of the instruction circuitry, an address control output connected to the control input of the address circuitry, and an address control input connected to the control output of the address circuitry.
Dependencies are inferred from the claim text.