Single precision floating-point data storing method and processor
AssigneeFujitsu Limited
InventorToshio Yoshida
Life of this patent
Estimating the term…
Abstract
A single-precision floating-point data storing method for use in a processor including a register, which has a size that can store double-precision floating-point data, for storing double-precision floating-point data and single-precision floating-point data comprises writing input single-precision floating-point data to the high-order half of the register, and writing all zeros to the low-order half of the register if a single-precision floating-point data process is specified.
Claims9
A single-precision floating-point data storing method for use in a processor including a register, which has a size that can store double-precision floating-point data, configured to store double-precision floating-point data and single-precision floating-point data, comprising:
- writing input single-precision floating-point data to a high-order half of the register, and writing all zeros to a low-order half of the register when a single-precision floating-point data process is specified and a first process is specified;
- and
- writing input single-precision floating-point data to the high-order half of the register, and writing no data to the low-order half of the register when the single-precision floating-point data process is specified and a second process is specified,
- wherein
- whether the writing the input single-precision floating point data to the high-order half of the register is the first process or the second process is determined based on results of decoding of an instruction.
A processor comprising:
- a register, which has a size that can store double-precision floating-point data, configured to store double-precision floating-point data and single-precision floating-point data;
- a decoder configured to perform decoding of an instruction;
- and
- a controlling unit configured to perform writing input single-precision floating-point data to a high-order half of the register, and writing all zeros to a low-order half of the register when a single-precision floating-point data process is specified and a first process is specified, or writing input single-precision floating-point data to the high-order half of the register, and writing no data to the low-order half of the register when the single-precision floating-point data process is specified and a second process is specified,
- wherein whether the writing the input single-precision floating point data to the high-order half of the register is the first process or the second process is determined based on results of decoding of an instruction.
Dependencies are inferred from the claim text.