Testing the compliance of a design with the synchronization requirements of a memory model

Apparatus for compliance testing of a circuit design, wherein the circuit design comprises a circuit that includes at least one processor and a memory, comprising:

• an input interface, which is arranged to accept a coverage model defined for a memory model of the circuit design, the memory model comprising synchronization mechanisms for synchronizing access to the memory by software instructions in different program threads running on the at least one processor, and which is arranged to accept a specification of synchronization-related parameters for at least one sequence of the software instructions in the different program threads, wherein the coverage model is defined as a multi-dimensional cross-product of different combinations of values of the synchronization-related parameters;
• a testing generator for generating at least one circuit design test program comprising at least two threads having parameter combinations selected based on the coverage model;
• and
• a testing processor, for testing the circuit design to determine if the circuit design complies with the synchronization mechanisms of the memory model using the coverage model by subjecting the circuit design to the at least one circuit design test program.

A computer software product for compliance testing of a circuit design wherein the circuit design comprises a circuit includes at least one processor and a memory, the product comprising a non-transitory computer-readable medium, in which program instructions are stored, which instructions, when read by a computer, cause the computer to perform steps of:

• accepting a coverage model defined for a memory model of the circuit design, the memory model comprising synchronization mechanisms for synchronizing access to the memory by software instructions in different program threads running on the at least one processor, and the coverage model defined as a multi-dimensional cross-product of different combinations of values of the synchronization-related parameters, to accept a specification of synchronization-related parameters for at least one sequence of the software instructions in the different program threads;
• generating at least one circuit design test program comprising at least two threads having parameter combinations selected based on the coverage model;
• and
• testing the circuit design to determine if the design complies with the synchronization mechanisms of the memory model using the coverage model by subjecting the circuit design to the at least one circuit design test program.