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US 8,411,812 B2Granted
Wide frequency range delay locked loop
AssigneeMosaid Technologies Incorporated
InventorsPeter Vlasenko, Dieter Haerle
Life of this patent
Estimating the term…
Abstract
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
Claims19
A memory device comprising:
- a delay locked loop;
- and
- an input pad capable of receiving an external clock signal for routing to the delay locked loop, and
- the delay locked loop being configured to synchronize an internal clock signal with the external clock signal, the delay locked loop comprising:
- a digital delay circuit configured to enable digital delay elements of the digital delay circuit in providing coarse phase adjustment in the delay locked loop;
- an analog delay circuit configured to provide fine phase adjustment in the delay locked loop in response to a control signal;
- a phase detector circuit configured to compare the external clock signal and the internal clock signal;
- and
- a lock detector circuit in communication with the phase detector circuit and the analog delay circuit, the lock detector circuit being configured to detect a condition signal resulting from an internal clock signal rising edge occurring after a rising edge of the external clock signal, and the lock detector circuit being further configured to detect another condition signal resulting from the internal clock signal rising edge occurring after a falling edge of the external clock signal, and in response to the lock detector circuit detecting that the condition signal and the another conditional signal are present, the lock detector circuit being further configured to:
- i) hold the digital delay circuit at a fixed delay;
- and ii) provide the control signal to the analog delay circuit.
8 more elements
A method for performing phase adjustment in a delay locked loop comprising:
- enabling digital delay elements of a digital delay circuit in providing coarse phase adjustment in the delay locked loop;
- in a phase detector circuit of the delay locked loop, comparing an external clock signal and an internal clock signal;
- in a lock detector circuit of the delay locked loop:
- detecting a condition signal resulting from an internal clock signal rising edge occurring after a rising edge of the external clock signal;
- detecting another condition signal resulting from the internal clock signal rising edge occurring after a falling edge of the external clock signal;
- and
- in response to detecting that the condition signal and the another conditional signal are present, holding the digital delay circuit at a fixed delay and providing a control signal to the analog delay circuit;
- and
- in an analog delay circuit of the delay locked loop, providing fine phase adjustment in response to the control signal.
6 more elements
Dependencies are inferred from the claim text.