Receiving circuit with adaptive synchronization and method thereof
AssigneeMStar Semiconductor, Inc.
InventorMeng Che Tsai
Life of this patent
Estimating the term…
Abstract
A circuit with adaptive synchronization and a method thereof is provided. The synchronous receiving circuit adaptively adjusts the timing of a clock signal generated therein for receiving data without accompanying a clock signal for synchronization. The synchronous receiving circuit includes a clock generator, an edge detector, a synchronization unit and a latch. The clock generator generates a first clock signal according to an input data signal. The edge detector detects edges to generate an indication signal. The synchronization unit is coupled to the clock generator and the edge detector, and adaptively adjusts the first clock signal according to the indication signal. The latch latches the input data signal according to the adjusted first clock signal.
Claims18
A receiving circuit with adaptive synchronization, comprising:
- a clock generator, for generating a first clock signal according to an input data signal;
- an edge detector, for performing edge detection on the input data signal to generate an indication signal;
- a synchronization unit, coupled to the clock generator and the edge detector, for adaptively adjusting the first clock signal according to the indication signal;
- and
- a latch, coupled to the synchronization unit, for latching the input data signal according to the adjusted first clock signal,
- wherein the clock generator synchronously generates a second clock signal according to the input data signal, a frequency of the second clock signal is n times that of the first clock signal, where n is a positive integer, the synchronization unit comprises a phase clock counter for updating a phase counter value according to the second clock signal, and the phase counter value represents a phase of the first clock signal.
A receiving method with adaptive synchronization, comprising steps of:
- generating, using a clock generator within a data communication receiver, a first clock signal according to an input data signal;
- performing edge detection on the input data signal to generate an indication signal;
- adaptively adjusting timing of the first clock signal according to the indication signal;
- synchronously generating a second clock signal according to the input data signal, a frequency of the second clock signal being n times of that of the first clock signal, where n is a positive integer;
- and
- updating a phase counter value according to the second clock signal, the phase counter value representing a phase of the first clock signal.
Dependencies are inferred from the claim text.