Multi-interface compatible bus over a common physical connection
AssigneeJuniper Networks, Inc.
InventorsDavid P. Chengson, Jaya Bandyopadhyay
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Abstract
A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.
Claims21
A system comprising:
- a first circuit board to:
- identify, when a second circuit board is inserted into a device connected to the first circuit board, whether the second circuit board, communicating with the first circuit board via a communication bus formed by a plurality of communication lines, is designed to communicate using a synchronous bus protocol or an asynchronous bus protocol by detecting an initial communication pattern;
- communicate with the second circuit board using the synchronous bus protocol when the second circuit board is designed to communicate using the synchronous bus protocol,
- when communicating using the synchronous bus protocol, the first circuit board being to:
- communicate with the second circuit board using all of the plurality of communication lines forming the bus, and
- configure a multiplexer of a multi-interface bus logic associated with the first circuit board to receive a clock signal from an oscillator;
- and
- communicate with the second circuit board using the asynchronous bus protocol when the second circuit board is designed to communicate using the asynchronous bus protocol,
- when communicating using the asynchronous bus protocol, the first circuit board being to:
- communicate with the second circuit board using a subset of the plurality of communication lines forming the bus, and
- configure the multiplexer of the multi-interface bus logic associated with the first circuit board to receive a second, different clock signal from a phase locked loop.
A network device comprising:
- a second card capable of communicating, asynchronously or synchronously, with a first card inserted into the network device through a bus formed by a plurality of communication lines, the second card to:
- determine whether the first card is designed to communicate synchronously or asynchronously,
- communicate with the first card using synchronous communications when the first card is designed to communicate synchronously, when communicating synchronously, the second card being to:
- use all of a set of logical communication lines, which are different than clock signal lines, of the plurality of communication lines forming the bus, and
- configure a multiplexer of a multi-interface bus logic associated with the first circuit board to receive a clock signal from an oscillator;
- and
- communicate with the first card using asynchronous communications when the first card is designed to communicate asynchronously, when communicating asynchronously, the second card being to:
- use a subset of the set of logical communication lines, and
- configure the multiplexer of the multi-interface bus logic associated with the first circuit board to receive a second, different clock signal from a phase locked loop.
A method implemented in a network device, the method comprising:
- detecting, by a first networking card, whether a second networking card, inserted into the network device and communicating with the first networking card via a communication bus formed by a plurality of communication lines, is a synchronous networking card or an asynchronous networking card;
- communicating, by the first networking card, synchronously with the second networking card based on detecting that the second networking card is a synchronous networking card, communicating synchronously including:
- communicating with the second networking card using all of the plurality of communication lines forming the bus, and
- configuring a multiplexer of a multi-interface bus logic associated with the first networking card to receive a clock signal from an oscillator;
- and
- communicating, by the first networking card, asynchronously with the second networking card based on detecting that the second networking card is an asynchronous networking card, communicating asynchronously including:
- communicating with the second networking card using a subset of the plurality of communication lines forming the bus, and
- configuring the multiplexer of the multi-interface bus logic associated with the first networking card to receive a second, different clock signal from a phase locked loop.
A network card for connection to an external bus, the network card comprising:
- a multiplexer to select between a first clock signal and second, different clock signal based on a type of external circuit board attached to the external bus;
- and logic to:
- determine whether the external circuit board is designed to communicate synchronously or asynchronously,
- receive, using all logical communication lines of a plurality of communication lines forming the external bus, data over the external bus by using the first clock signal to recover a first sampling clock signal from a data signal of the external bus when the external circuit board is designed to communicate synchronously;
- and
- receive, using a subset of the plurality of logical communication lines forming the external bus, data over the external bus by using the second clock signal to recover a second sampling clock signal from a data signal of the external bus when the external circuit board uses an asynchronous bus.
Dependencies are inferred from the claim text.