Semiconductor device capable of adjusting memory page size based on a row address and a bank address
AssigneeSamsung Electronics Co., Ltd.
InventorsHoon Lee, Uk Song Kang, Hoe Ju Chung
Life of this patent
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Abstract
A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.
Claims20
A semiconductor device comprising a plurality of stacked semiconductor chips each comprising a plurality of banks, the plurality of semiconductor chips respectively comprising page size controllers configured to select one semiconductor chip among the plurality of semiconductor chips based on a chip selection address including a part of a bank selection address and a part of a row address and to enable at least two banks among the plurality of banks comprised in the selected semiconductor chip based on a remaining part of the bank selection address to increase a page size.
A semiconductor device comprising:
- a plurality of stacked semiconductor chips each including a plurality of banks, the plurality of semiconductor chips respectively comprising page size controllers configured to select at least two semiconductor chips among the plurality of semiconductor chips based on a part of a row address and to enable one bank among the plurality of banks comprised in each of the selected semiconductor chips based on a bank selection address.
Dependencies are inferred from the claim text.