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US 8,411,525 B2Granted
Memory circuits having a diode-connected transistor with back-biased control
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSteven Swei, David B. Scott
Life of this patent
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Abstract
A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.
Claims20
A memory circuit comprising:
- at least one memory array;
- at least one sleep transistor electrically coupled to both the at least one memory array and a first power line for providing a first power voltage;
- at least one diode-connected transistor is turned on and electrically coupled to both the at least one memory array and the first power line during an entire period of operation;
- and
- a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.
2 more elements
A memory circuit comprising:
- at least one memory array;
- at least one sleep transistor electrically coupled to both the at least one memory array and a first power line for providing a first power voltage, wherein the at least one sleep transistor is turned off during a data retention mode;
- at least one diode-connected transistor is turned on and electrically coupled to both the at least one memory array and the first power line during an entire period of operation, wherein the at least one diode-connected transistor is turned on during the data retention mode such that the at least one memory array is electrically coupled to the first power line via the at least one diode-connected transistor;
- and
- a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor, wherein the back-bias circuit is configured to provide a voltage to the bulk of the at least one diode-connected transistor such that a source and the bulk of the at least one diode-connected transistor are reverse biased during the data retention mode.
2 more elements
A method of operating a memory circuit during a data retention mode, the method comprising:
- turning off at least one sleep transistor during a data retention mode, the at least one sleep transistor is electrically coupled to both at least one memory array and a first power line for providing a first power voltage;
- turning on at least one diode-connected transistor during the data retention mode, wherein the at least one diode-connected transistor is electrically coupled to both the at least one memory array and the first power line during an entire period of operation;
- and
- reverse biasing a source and a bulk of the at least one diode-connected transistor during the data retention mode.
1 more element
Dependencies are inferred from the claim text.