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US 8,411,523 B2Granted
Reduced current requirements for DRAM self-refresh modes via staggered refresh operations of subsets of memory banks or rows
AssigneeIntel Corporation
InventorKuljit S. Bains
Life of this patent
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Abstract
Embodiments of the invention describe systems, methods, and apparatuses to reduce the instantaneous power necessary to execute a DRAM device initiated self-refresh. Embodiments of the invention describe a DRAM device enabled to stagger self-refreshes between a plurality of banks. Staggering self-refreshes between banks reduces the current required for a DRAM self-refresh, thus reducing the amount of current required by the DRAM device.
Claims17
A system comprising:
- a dynamic random access memory (DRAM) device to execute a self-refresh mode, the DRAM device including a plurality of banks, each bank to include a plurality of rows, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the banks;
- a memory controller operatively coupled to the DRAM device;
- and
- logic, operatively coupled to the DRAM device and the memory controller, to:
- determine the number of banks included in the DRAM device,
- determine characteristics of power supplied to the DRAM device, and
- determine a plurality of subsets of banks or rows to be concurrently refreshed in the self-refresh mode, wherein determining the plurality of subsets to be concurrently refreshed is based, at least in part, on the characteristics of power supplied to the DRAM device;
- the DRAM device to execute the self-refresh mode for each of the plurality of subsets in a staggered fashion.
5 more elements
A method comprising:
- determining the number of banks included in a DRAM device, the DRAM device to include a plurality of banks, each bank to include a plurality of rows;
- determining characteristics of power supplied to the DRAM device;
- determining a plurality of subsets of banks or rows to be concurrently refreshed in a self-refresh mode based, at least in part, on the characteristics of power supplied to the DRAM device, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the banks;
- and
- executing the self-refresh mode for each of the plurality of subsets in a staggered fashion.
2 more elements
An apparatus comprising:
- a plurality of DRAM banks, each DRAM bank to include a plurality of rows;
- a first logic, operatively coupled to the DRAM banks, to determine characteristics of power supplied to the apparatus;
- and
- a second logic, operatively coupled to the DRAM banks and the first logic, to:
- execute a self-refresh mode for the plurality of subsets of DRAM banks or rows in a staggered fashion, the self-refresh mode to include a plurality of commands, each command to refresh rows of one of the DRAM banks;
- and
- determine the plurality of subsets to be refreshed based, at least in part, on the characteristics of power supplied to the apparatus.
4 more elements
Dependencies are inferred from the claim text.