Semiconductor device

A semiconductor device comprising:

• first and second memory cells;
• first and second bit lines coupled to the first and second memory cells, respectively;
• a well defined by first and second edge lines opposed to each other;
• first and second transistors formed in the well such that the first and second transistors are arranged adjacently to the first and second edge lines, respectively, the first transistor operating to precharge of the first bit line, and the second transistor operating to precharge of the second bit line;
• and
• third and fourth transistors formed in the well such that the third and fourth transistors are between the first and second transistors, and gates of the third and fourth transistors being coupled to the first and second bit lines, respectively.

A semiconductor device comprising:

• a first well including first, second and third portions, the third portion being between the first and second portions;
• first, second, third and fourth bit lines;
• first and second transistors formed in the first and second portions of the first well, respectively, each of the first and second transistors including a gate supplied with a precharge signal;
• and
• third, fourth, fifth and sixth transistors each formed in the third portion of the first well, the third, fourth, fifth and sixth transistors being coupled at gates thereof to the first, second, third and fourth bit lines, respectively, and each of the first to sixth transistors is of a first channel type.

A semiconductor device comprising:

• a first memory cell area, a second memory cell area and a sense amplifier area between the first and second memory cell areas;
• the first memory cell area comprising:
• first and second memory cells;
• and
• first and second bit lines connected respectively to the first and second memory cells and each extended toward the sense amplifier area;
• the second memory cell area comprising:
• third and fourth memory cells;
• and
• third and fourth bit lines connected respectively to the third and fourth memory cells and each extended toward the sense amplifier area;
• and
• the sense amplifier area comprising:
• a first sense amplifier connected respectively to the first and third bit lines to amplify a potential difference therebetween, the first sense amplifier including a first pair of transistors each of a first channel type and a second pair of transistors each of a second channel type;
• a second sense amplifier connected respectively to the second and fourth bit lines to amplify a potential difference therebetween, the second sense amplifier including a third pair of transistors each of the first channel type and a fourth pair of transistors each of the second channel type;
• a first precharge circuit coupled to the first and third bit lines to precharge each of the first and third bit lines;
• a second precharge circuit coupled to the second and fourth bit lines to precharge each of the second and fourth bit lines;
• the second pair of transistors and the fourth pair of the transistors being disposed between the first and second precharge circuits;
• the first pair of transistors being disposed between the first precharge circuit and the first memory cell area;
• and
• the third pair of transistors being disposed between the second precharge circuit and the second memory cell area.