Semiconductor memory device and method of reducing consumption of standby current therein
AssigneeSamsung Electronics Co., Ltd.
InventorsMyung-Jae Lee, Sang Seok Kang, Jong Hyoung Lim
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Abstract
A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit.
Claims16
A semiconductor memory device, comprising:
- a memory array including a plurality of bit lines and a plurality of dummy bit lines;
- a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, the plurality of voltage levels including a ground voltage level, a power voltage level, and a plurality of voltage levels between the ground voltage level and the power voltage level;
- and
- a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines, each of the standby currents being generated by each of the bias voltages applied by the bias application unit.
A semiconductor memory device, comprising:
- a mode register set (MRS) in which a plurality of operation modes corresponding to a plurality of voltage levels are set and stored;
- a fuse configured to allow a bias voltage to be supplied to each of a plurality dummy bit lines, to the bias voltage having one of the voltage levels set in any one of the plurality of operation modes stored in the MRS;
- and
- a controller configured to measure a value of at least one of standby currents between the plurality of dummy bit lines and a plurality of bit lines, each of the standby currents generated by each of voltage supplied by the fuse, and to control the fuse to allow a voltage generating a minimum standby current to be supplied to each of the plurality of dummy bit lines.
A method of reducing a standby current in a semiconductor memory device that comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, the method comprising:
- supplying bias voltages having a plurality of voltage levels to the plurality of dummy bit lines;
- measuring a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines, each of the standby currents being generated by each of the bias voltages;
- and
- supplying a bias voltage having any one of the plurality of voltage levels to each of the plurality of dummy bit lines, based on a measured value of a standby current generated by the bias voltage having any one of the plurality of voltage levels.
A method of reducing a standby current in a semiconductor memory device that comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, the method comprising:
- setting and storing a plurality of operation modes corresponding to a plurality of voltage levels in a MRS;
- allowing a bias voltage to be supplied to each of a plurality dummy bit lines with a fuse, the bias voltage having one of the voltage levels set in any one of the plurality of operation modes stored in the MRS;
- and
- measuring a value of at least one of standby currents between the plurality of dummy bit lines and a plurality of bit lines, each of the standby currents generated by each of voltage supplied by the fuse;
- and
- controlling the fuse to allow a voltage generating a minimum standby current to be supplied to each of the plurality of dummy bit lines.
Dependencies are inferred from the claim text.