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US 8,411,518 B2Granted
Memory device with boost compensation
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsDhori Kedar Janardan, Rakesh Kumar Sinha, Sachin Gulyani
Life of this patent
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Abstract
A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.
Claims37
A memory circuit comprising:
- a memory cell configured to be re-writable;
- a write enable circuit configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal;
- a negative boost circuit configured to apply a negative boost charge to at least one of the pair of bit lines;
- and
- a charge supply controller configured to control application of the negative boost charge by the negative boost circuit dependent on both the temperature of the memory circuit and the potential difference supply of the memory circuit.
2 more elements
A method of operating a memory circuit comprising:
- controlling charge of a negative boost supplied to at least one of a pair of bit lines coupled to a memory cell of a memory circuit dependent on both the temperature of the memory circuit and the potential difference supply of the memory circuit.
A memory circuit, comprising:
- a memory cell configured to be re-writable;
- a write enable circuit configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal;
- a charge supply circuit configured to supply a charge to at least one of the pair of bit lines;
- and
- a charge supply controller configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit;
- wherein the charge supply controller comprises a charge compensation circuit including a current source in the form of a sub-threshold biased transistor coupled to the charge supply circuit and configured to control the supply of charge to the at least one bit line dependent on the temperature of the sub-threshold biased transistor.
3 more elements
A memory circuit, comprising:
- a memory cell configured to be re-writable;
- a write enable circuit configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal;
- a charge supply circuit configured to supply a charge to at least one of the pair of bit lines;
- and
- a charge supply controller configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit;
- wherein the charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at the potential on the at least one bit line and comprises:
- a potential threshold determiner configured to determine when at least one bit line potential is less than a defined potential value;
- and
- a charge supply driver configured to selectively couple the charge supply circuit to at least one of the pair of bit lines dependent on the potential threshold determiner.
6 more elements
A memory circuit, comprising:
- a memory cell configured to be re-writable;
- a write enable circuit configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal;
- a charge supply circuit configured to supply a charge to at least one of the pair of bit lines;
- and
- a charge supply controller configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit;
- wherein the charge supply controller is configured to control the timing of the charge supply circuit to supply the charge dependent at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.
3 more elements
A method of operating a memory circuit, comprising:
- controlling a charge boost supplied to at least one of the pair of bit lines coupled to a memory cell dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit;
- wherein controlling a charge boost supplied to at least one of the pair of bit lines comprises coupling a current source to a charge supply circuit for supplying the charge boost;
- and
- wherein coupling the current source comprises coupling a sub-threshold biased transistor for limiting the supply of charge to the at least one bit line substantially dependent on the temperature of the transistor.
1 more element
Dependencies are inferred from the claim text.