Delay locked loop circuit including delay line with reduced sensitivity to variation in PVT
AssigneeSamsung Electronics Co., Ltd.
InventorSeok-Woo Choi
Life of this patent
Estimating the term…
Abstract
A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.
Claims19
A delay locked loop circuit for use in a semiconductor device, the delay locked loop circuit comprising:
- a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal;
- a control circuit unit for controlling a delay line in response to the detection signal;
- a delay line for delaying the input clock signal by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line;
- and
- a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal,
- wherein the delay line further comprises:
- two or more inverter circuits in series;
- a first node at a first inverter circuit for receiving an the input clock signal;
- a second node at the first inverter circuit for outputting an inverted delayed clock signal;
- a first set of pull-up transistors, each having a gate connected to the first node and a drain connected to a third node;
- a first resistor connected at one end to the second node and connected at the other end to the third node;
- a set of pull-down transistors, each having a gate connected to the first node drain connected to a fourth node;
- and
- a second resistor connected at one end to the second node and connected at the other end to the fourth node.
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells arranged in a matrix;
- a read/write circuit connected to the memory cells in the memory cell array, the read/write circuit including at least one of an input buffer and an output buffer;
- and
- a delay locked loop circuit configured to output an output clock signal that is delay-locked as an input clock signal to the read/write circuit,
- wherein the delay locked loop circuit includes:
- a phase detector configured to compare the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and to output a detection signal;
- a control circuit for controlling a delay locked operation in response to the detection signal;
- a delay line for delaying the input clock signal by a predetermined amount of delay in response to codes applied to control transistors in the delay line;
- and
- a replica circuit configured to have the same delay conditions as those of an actual clock path to the read/write circuit of the semiconductor memory device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal, wherein as a result of using the codes, the delay line has reduced sensitivity to variations in PVT,
- wherein the delay line further comprises:
- a first inverter circuit comprising:
- a first node for receiving the input clock signal,
- a second node for outputting an inverted delayed input clock signal,
- a set of pull-up transistors, each having a gate connected to the first node and a drain connected to a third node,
- a first resistor connected at one end to the second node and connected at the other end to the third node,
- a set of pull-down transistors, each having a gate connected to the first node and a drain connected to a fourth node, and
- a second resistor connected at one end to the second node and connected at the other end to the fourth node.
A delay line circuit for delaying an input clock signal, comprising a set of inverter circuits connected in series, and including:
- an initial inverter circuit, including:
- a first node for receiving an input clock signal that is also input into a phase detector,
- a second node for outputting a delayed inverted input clock signal to another inverter circuit,
- a first set of pull-up transistors, each having a gate connected to the first node and a source connected to a control transistor, and
- a first set of pull-down transistors, each having a gate connected to the first node and a source connected to a control transistor;
- and
- a final inverter circuit, including:
- a third node for receiving an inverted delayed input clock signal from another of the set of inverter circuits,
- a fourth node for outputting a delay clock signal that is output to a replica circuit and to an output clock buffer for use in a semiconductor device,
- a second set of pull-up transistors, each having a gate connected to the third node and a source connected to a control transistor, and
- a second set of pull-down transistors, each having a gate connected to the third node and a source connected to a control transistor.
Dependencies are inferred from the claim text.