Memory cell having reduced circuit area
AssigneeSitronix Technology Corp.
InventorMin-Nan Liao
Life of this patent
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Abstract
The present invention relates to a memory cell having a reduced circuit area, which comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled to a readline and controlled by a wordline. The second transistor is coupled between the first transistor and a low-voltage power supply. The third transistor is coupled to the second transistor and controlled by a bitline. The third transistor controls turn-on and cutoff of the second transistor. Besides, the fourth transistor is coupled to the third transistor and a writeline, and is controlled by the wordline. Thereby, according to the present invention, four transistors form a memory cell, and the objective of saving circuit area can be achieved.
Claims11
A memory cell having a reduced circuit area, comprising:
- a first transistor, coupled to a readline, and controlled by a wordline;
- a second transistor, coupled between said first transistor and a low-voltage power supply;
- a third transistor, coupled to said second transistor, or controlled by a bitline or controlling turn-on/cutoff of said second transistor;
- and
- a fourth transistor, coupled to said third transistor and a writeline, and controlled by said wordline.
Dependencies are inferred from the claim text.