Semiconductor memory

A high-speed startup drive circuit for use in a semiconductor memory, said semiconductor memory including:

• a memory cell having a data line;
• a sense amplifier that generates information data having a logic level corresponding to a result of comparing, in magnitude, a value of a current supplied to the data line of the memory cell in response to a read signal and a predetermined threshold value;
• a control unit that generates an enable signal indicating one of an activation state and a deactivation state;
• and
• a reference amplifier that, when said enable signal has shifted from the deactivation state to the activation state, generates a reference voltage having a voltage value equal to said predetermined threshold value and supplies the reference voltage to said sense amplifier via a reference voltage supply line,
• said high-speed startup drive circuit comprising:
• a first FET that is turned on to apply a predetermined first voltage onto a first line when said enable signal indicates the deactivation state;
• a second FET that is turned on to apply ground potential onto the first line when the voltage on said reference voltage supply line is higher than a gate threshold voltage value;
• a third FET that is turned on to generate said first voltage when said enable signal indicates the activation state;
• and
• a fourth FET that is turned off when said first line is at ground potential and is turned on to supply said first voltage from said third FET onto said reference voltage supply line when said first voltage is applied onto said first line.