Multi-chip package including output enable signal generation circuit and data output control method thereof
AssigneeSK hynix Inc.
InventorsKi Han Kim, Hyun Woo Lee
Life of this patent
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Abstract
An output enable signal generation circuit includes a latency decoder, a latch unit, a latency multiplexer, and an enable setting unit. The latency decoder is configured to decode a mode register set code and generate first and second CAS latency information. The latch unit is configured to output the latched first and second latency information as first and second latency signals. The latency multiplexer is configured to output the first or second latency signal as an output CAS latency signal in response to a chip select signal. The enable setting unit is configured to set an enable timing of an output enable signal.
Claims16
An output enable generation circuit comprising:
- a latency signal generation unit outputting a first latency signal for a first latency and outputting a second latency signal for a second latency;
- and
- an output enable signal generation unit outputting an output enable signal, wherein an enable timing of the output enable signal is set in response to the first latency signal when the first latency is selected or in response to the second latency signal when the second latency is selected,
- wherein the first and second latencies are caused by different data path lengths of two chips in a multichip package, and wherein the first or second latency is selected in response to a chip select signal received by the output enable signal generation unit.
A multi-chip package in which a slave chip is stacked on a master chip and data is outputted through the master chip during read operations, the multi-chip package comprising:
- an output enable signal generation circuit configured to generate first and second latency signals from first and second latency information, generate an output enable signal whose enable timing is set according to the first latency signal during the read operation of the master chip, and generate an output enable signal whose enable timing is set according to the second latency signal during the read operation of the slave chip.
A data output control method of a multi-chip package comprising a first chip and a second chip, the data output control method comprising:
- generating first and second latency signals determined based on a mode register set operation;
- and outputting accessed data of the first chip during a read operation of the first chip at an enable timing of an output enable signal set by the first latency signal, and outputting accessed data of the second chip during a read operation of the second chip at an enable timing of the output enable signal set by the second latency signal.
Dependencies are inferred from the claim text.