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US 8,411,513 B2Granted
Techniques for providing a semiconductor memory device having hierarchical bit lines
AssigneeMicron Technology, Inc.
InventorEric Carman
Life of this patent
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Abstract
Techniques for providing a semiconductor memory device having hierarchical bit lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells and a plurality of local bit lines coupled directly to the plurality of memory cells. The semiconductor memory device may also include a multiplexer coupled to the plurality of local bit lines and a global bit line coupled to the multiplexer.
Claims19
A semiconductor memory device comprising:
- a plurality of memory cells;
- a plurality of local bit lines coupled directly to the plurality of memory cells;
- a multiplexer coupled to the plurality of local bit lines, wherein the multiplexer comprises a plurality of hold transistors each configured to apply a holding signal to a respective memory cell during a hold operation;
- and
- a global bit line coupled to the multiplexer.
2 more elements
Dependencies are inferred from the claim text.