Semiconductor memory apparatus
AssigneeSK hynix Inc.
InventorsChul Kim, Jong Chern Lee
Life of this patent
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Abstract
A semiconductor memory apparatus includes: a memory cell array including a plurality of memory cells; a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line; a plurality of local input/output lines coupled to the BLSA; and a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines.
Claims9
A semiconductor memory apparatus comprising:
- a memory cell array including a plurality of memory cells;
- a bit line sense amplifier (BLSA) coupled to the memory cells in the memory cell array through a bit line;
- a plurality of local input/output lines coupled to the BLSA;
- a switching unit coupled to the local input/output lines and configured to select a part of the local input/output lines;
- and
- a column decoder configured to output a first column select signal for driving the BLSA and a second column select signal for driving the switching unit, in response to a column address and a column pulse signal.
A semiconductor memory apparatus including a plurality of banks, wherein each of the banks comprises a plurality of memory cell array blocks, and wherein each of the memory cell array blocks comprises:
- a bit line sense amplifier (BLSA) driven in response to a first column select signal,
- a switching unit configured to selectively output a half of data signals amplified by the BLSA in response to a second column select signal,
- a main amplifier configured to amplify the data signals which are selectively outputted from the switching unit, and
- a column decoder configured to output the first and second column select signals in response to a column address and a column pulse signal.
A semiconductor memory apparatus having a through-silicon via TSV structure in which at least two semiconductor memory chips are stacked, wherein each of the semiconductor memory chips includes a plurality of memory cell array blocks, and wherein each of the memory cell array blocks comprises:
- a switching unit configured to select a part of output signals of a bit line sense amplifier (BLSA),
- a plurality of main amplifiers coupled to the switching unit, and
- a column decoder configured to output a first column select signal for driving the BLSA and a second column select signal for driving the switching unit, in response to a column address and a column pulse signal, wherein the switching unit is driven according to the second column select signal and selectively outputs a half of the output signals of the BLSA.
Dependencies are inferred from the claim text.