Programming method for non-volatile memory device

A method of programming memory cells of a multi-level cell non-volatile memory, the method comprising:

• applying a first programming pulse to a wordline of the non-volatile memory device and a first bitline voltage to at least one first bitline associated with the wordline corresponding to a first latch value;
• applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline associated with the wordline corresponding to a second latch value, and a third bitline voltage to at least one third bitline associated with the wordline corresponding to a third latch value,
• wherein a voltage level of the second programming pulse is different from a level of the first programming pulse,
• the second bitline voltage is different from the third bitline voltage if the second latch value and third latch value are different,
• the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,
• the second programming pulse is applied to the wordline successively after the first programming pulse,
• after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the wordline successively, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with a data value being programmed to the memory cell, and
• the first latch value, the second latch value and the third latch value are a value stored in at least one latch among a plurality of latches of a page buffer of the memory.

A method of programming a non-volatile memory device comprising a first memory cell connected to a wordline and a first bitline and a second memory cell connected to the wordline and a second bitline, wherein the first memory cell and second memory cell are multi-level non-volatile memory cells capable of being programmed to 1st through Mth data values, the method comprising:

• performing a programming operation during which the first memory cell is programmed to an ith data value among the 1st through Mth data values using a first programming pulse applied to the wordline, and the second memory cell is programmed to a jth data value among the 1st through Mth data values using a second programming pulse different from the first programming pulse and applied to the wordline, the programming operation comprising:
• simultaneously applying a first bitline voltage having a first level and corresponding to the ith data value to the first bitline, and a second bitline voltage having a second level different from the first level and corresponding to the jth data value to the second bitline;
• and
• performing a verifying operation on the first memory cell and second memory cell, wherein execution timing for the verifying operation varies in relation to the 1st through Mth data values,
• the second programming pulse is applied to the wordline successively after the first programming pulse, and
• the verifying operation is performed after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the wordline successively, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with a data value being programmed to the memory cell.

A method of programming memory cells of a multi-level cell non-volatile memory to one of a plurality of data values, the method comprising:

• applying a first programming pulse to a wordline of the non-volatile memory device, a first bitline voltage to at least one first bitline associated with the wordline corresponding to a first data value among a plurality of data values, a second bitline voltage to at least one second bitline associated with the wordline corresponding to a second data value among the plurality of data values;
• applying a second programming pulse to the wordline, a third bitline voltage to at least one third bitline associated with the wordline corresponding to a third data value among the plurality of data values,
• wherein a voltage level of the second programming pulse is different from a level of the first programming pulse,
• the first bitline voltage is different from the second bitline voltage if the first data value and second data value are different,
• the first bitline voltage is applied to the at least one first bitline and the second bitline voltage is applied to the at least one second bitline simultaneously,
• the second programming pulse is applied to the wordline successively after the first programming pulse, and
• after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the wordline, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with a data value being programmed to the memory cell.