Memory base cell and memory bank

A memory bank having a plurality of memory base cells distributed along a plurality of columns and a plurality of lines, the memory bank comprising:

• a plurality of line decoders configured to address a line to select a given memory base cell;
• a plurality of column decoders configured to address a column to select the given memory base cell;
• a writing port for the plurality of memory base cells;
• a reading port for the plurality of memory base cells;
• an address bus configured to address the plurality of memory base cells;
• a control bus configured to select an operation to be carried out on an addressed memory base cell of the plurality thereof;
• each memory base cell of the plurality thereof comprising
• a writing data line and a reading data line;
• a bistable element comprising an input node operatively coupled to the writing data line, an output node operatively coupled to the reading data line, and a first inverter and a second inverter arranged in a feedback configuration with respect to one another between the input node and the output node,
• an input transfer element operatively coupled between the writing data line and the input node of the bistable element and configured to transfer a bit of information from the writing data line to the bistable element, the input transfer element comprising a first control terminal configured to receive a writing enabling logic signal, and a second control terminal configured to receive a writing enabling denied logic signal,
• the second inverter of the bistable element comprising a first writing enabling terminal configured to receive the writing enabling logic signal and a second writing enabling terminal configured to receive the writing enabling denied logic signal so that the second inverter of the bistable element is disabled for writing when the input transfer element is enabled for writing the bit of information.

A method of making a memory base cell for storing at least one bit of information, comprising:

• coupling an input node of a bistable element to a writing data line, and coupling an output node of the bistable element to a reading data line;
• arranging a first inverter and a second inverter of the bistable element in a feedback configuration with respect to one another between the input node and the output node;
• coupling an input transfer element between the writing data line and the input node of the bistable element to transfer a bit of information from the writing data line to the bistable element, the input transfer element comprising a first control terminal to receive a writing enabling logic signal, and a second control terminal to receive a writing enabling denied logic signal;
• the second inverter of the bistable element comprising a first writing enabling terminal to receive the writing enabling logic signal and a second writing enabling terminal to receive the writing enabling denied logic signal so that the second inverter of the bistable element is disabled for writing when the input transfer element is enabled for writing the bit of information.