Semiconductor memory device and method of writing into the same

A semiconductor memory device comprising:

• a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage;
• a first transistor comprising a drain terminal connected to one terminal of the resistance memory element and a source terminal connected to a reference voltage;
• a second transistor comprising a source terminal connected to the other terminal of the resistance memory element;
• and
• a control circuit which controls a channel resistance of the first transistor at a value which is sufficiently smaller than a resistance value of the resistance memory element in the high resistance state and is sufficiently larger than a resistance value of the resistance memory element in the low resistance state by controlling a first drive voltage to be applied to a gate terminal of the first transistor, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from the high resistance state to the low resistance state, and which clamps a voltage to be applied to said other terminal of the resistance memory element at a value which is not less than a reset voltage of the resistance memory element and less than a set voltage of the resistance memory element by controlling a second drive voltage to be applied to a gate terminal of the second transistor so as to be set at a value which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage of the second transistor, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from the low resistance state to the high resistance state.

A semiconductor memory device comprising:

• a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage;
• a first transistor comprising a drain terminal connected to one terminal of the resistance memory element and a source terminal connected to a reference voltage;
• a second transistor comprising a source terminal connected to the other terminal of the resistance memory element;
• and
• a control circuit which clamps a voltage to be applied to said other terminal of the resistance memory element at a value which is not less than a reset voltage of the resistance memory element and less than a set voltage of the resistance memory element by controlling a second drive voltage to be applied to a gate terminal of the second transistor so as to be set at a value which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage of the second transistor, when a write voltage is applied to the resistance memory element via the second transistor to switch the resistance memory element from the low resistance state to the high resistance state.

A semiconductor memory device comprising:

• a plurality of memory cells arranged in a matrix and each of which comprises a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage;
• a plurality of bit lines extended in a first direction and arranged in parallel with each other, each of the bit lines being connected to the other terminals of the resistance memory elements of the memory cells arranged in the first direction;
• a plurality of word lines extended in a second direction crossing the first direction and arranged in parallel with each other, each of the word line being connected to gate terminals of the first transistors of the memory cells arranged in the second direction;
• a plurality of second transistors , each of the second transistors being connected to each of the plurality of bit lines, each of the second transistors comprising a source terminal connected via the bit line to the other terminals of the resistance memory elements of the memory cells arranged in the first direction;
• and
• a control circuit which controls a channel resistance of the first transistor of an arbitrary one of the plurality of memory cells at a value which is sufficiently smaller than a resistance value of the resistance memory element in the high resistance state and is sufficiently larger than a resistance value of the resistance memory element in the low resistance state by controlling a first drive voltage to be applied to the word line associated with the arbitrary memory cell, when the resistance memory element of the arbitrary memory cell is switched from the high resistance state to the low resistance state, and which clamps a voltage to be applied to said other terminal of the resistance memory element of an arbitrary one of the plurality of memory cells at a value which is not less than a reset voltage of the resistance memory element and less than a set voltage of the resistance memory element by controlling a second drive voltage to be applied to a gate terminal of the second transistor so as to be set at a value which is not less than a total of the reset voltage and a threshold voltage of the second transistor and is less than a total of the set voltage and the threshold voltage of the second transistor, when the resistance memory element of the arbitrary memory cell is switched from the low resistance state to the high resistance state.