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US 8,411,482 B2Granted
Programmable read only memory
AssigneeIntel Corporation
InventorsZhanping Chen, Sarvesh Kulkarni, Kevin Zhang
Life of this patent
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Abstract
A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
Claims24
An apparatus comprising:
- a plurality of interconnected cells arranged as a column, wherein respective ones of the plurality of cells includes a fuse and a first transistor of a first type, the first transistor including a first terminal, a second terminal, and a third terminal, and the fuse including a fourth terminal and a fifth terminal;
- and
- a column selection logic coupled to the plurality of cells configured to facilitate selective programming of one or more fuses correspondingly associated with one or more of the plurality of cells,
- wherein the first terminal is coupled to a voltage supply terminal, the second terminal is coupled to the fourth terminal, and the fifth terminal is coupled to the column selection logic,
- wherein the column selection logic includes a second transistor of a second type, and
- wherein one or more first transistors associated with the one or more of the plurality of cells are respectively conductively coupled to the second transistor during programming of the one or more fuses to form one or more conductive paths with reduced parasitic resistances.
3 more elements
A method comprising:
- receiving a program voltage, from a voltage supply terminal, by each one of a plurality of cells arranged as a column,
- wherein the each one of the plurality of cells includes a fuse coupled with a first transistor of a first type, the first transistor including a first terminal, a second terminal, and a third terminal, and the fuse including a fourth terminal and a fifth terminal,
- wherein the column of cells is coupled to a column selection logic including a second transistor of a second type, and
- wherein the first terminal is coupled to the voltage supply terminal, the second terminal is coupled to the fourth terminal, and the fifth terminal is coupled to the column selection logic;
- and
- switching on or off the second transistor to facilitate programming of one or more fuses of one or more cells among the column of cells,
- wherein, during the programming of one or more fuses, one or more corresponding first transistors of the one or more cells are respectively coupled to the second transistor to form one or more conductive paths with reduced parasitic resistances.
4 more elements
A system comprising:
- a memory device comprising:
- a plurality of interconnected cells arranged in a column, wherein respective ones of the plurality of cells include a fuse and a first transistor of a first type, the first transistor including a first terminal, a second terminal, and a third terminal, and the fuse including a fourth terminal and a fifth terminal, and
- a column selection logic coupled to the plurality of interconnected cells configured to facilitate selective programming one or more fuses associated with one or more of the plurality of cells,
- wherein the first terminal is coupled to a voltage supply terminal, the second terminal is coupled to the fourth terminal, and the fifth terminal is coupled to the column selection logic,
- wherein the column selection logic includes a second transistor of a second type, and
- wherein one or more first transistors associated with the one or more of the plurality of cells are respectively conductively coupled to the second transistor during programming of the one or more fuses to form one or more conductive paths with reduced parasitic resistances;
- a processor coupled to the memory device and configured to further facilitate programming of the memory device;
- and
- one or more mass storage devices communicatively coupled to the processor.
6 more elements
Dependencies are inferred from the claim text.