Memory circuits, systems, and methods for routing the memory circuits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng Hung Lee, Jui-Che Tsai, Ching-Wei Wu, Kuang Ting Chen
Life of this patent
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Abstract
A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array.
Claims18
A memory circuit comprising:
- a first memory array, the first memory array including at least one first memory cell for storing a first datum, the at least one first memory cell being coupled with a first word line and a second word line of the first memory array;
- and
- a second memory array coupled with the first memory array, the second memory array including at least one second memory cell for storing a second datum, the at least one second memory cell being coupled with a third word line and a fourth word line of the second memory array,
- wherein the first word line is coupled with the third word line and the first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array, and the second word line and the fourth word line extend in parallel in a routing direction across the first memory array and the second memory array.
A system comprising:
- a processor;
- and
- a memory circuit coupled with the processor, the memory circuit comprising:
- a first memory array, the first memory array including at least one first memory cell for storing a first datum, the at least one first memory cell being coupled with a first word line and a second word line of the first memory array;
- and
- a second memory array coupled with the first memory array, the second memory array including at least one second memory cell for storing a second datum, the at least one second memory cell being coupled with a third word line and a fourth word line of the second memory array,
- wherein the first word line is coupled with the third word line and the first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array, and the second word line and the fourth word line extend in parallel in a routing direction across the first memory array and the second memory array.
A method for routing word lines of a memory circuit, the method comprising:
- routing a first word line and a second word line of a first memory array, the first word line and the second word line coupled with at least one first memory cell of the first memory array, and the at least one first memory cell being capable of storing a first datum;
- and
- routing a third word line and a fourth word line of a second memory array, the third word line and the fourth word line coupled with at least one second memory cell of the second memory array, and the second memory array being coupled with the first memory array, the at least one second memory cell being capable of storing a second datum,
- wherein the first word line is coupled with the third word line and the first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array, and the second word line and the fourth word line extend in parallel in a routing direction across the first memory array and the second memory array.
Dependencies are inferred from the claim text.