Three-dimensional stacked semiconductor integrated circuit
AssigneeSK hynix Inc.
InventorsTae Sik Yun, Young Jun Ku
Life of this patent
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Abstract
Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices.
Claims19
A three-dimensional stacked semiconductor integrated circuit comprising:
- a master slice;
- a plurality of slave slices;
- and
- a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices, at least one of the plurality of through-silicon vias being configured to transmit an operation control signal from the master slice to the plurality of slave slices,
- wherein the at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices,
- wherein one of the plurality of slave slices is configured to be selected by a slave selection signal from the master slice, and selected the one of the plurality of slave slices is configured to receive the operation control signal.
A three-dimensional stacked semiconductor integrated circuit comprising:
- a master slice configured to generate a master active control signal and a slice selection signal in response to a command and generate a pulse signal based on the master active control signal;
- a plurality of slave slices configured to be selected one of the plurality of slave slices by the slice selection signal, and selected the one of the plurality of slave slices is configured to convert the pulse signal to a slave active control signal;
- and
- a plurality of through-silicon vias configured to be commonly connected between the master slice and the plurality of slave slices for transferring the pulse signal and the slice selection signal.
A method of controlling a stacked semiconductor integrated circuit having a master slice and a plurality of slave slices, the method comprising:
- generating a master active control signal and a slice selection signal in response to a command;
- generating a pulse signal based on the master active control signal in the master slice;
- transmitting the master active control signal and the slice selection signal to the plurality of slave slices through a plurality of through-silicon vias shared by the plurality of slave slices;
- and
- converting the pulsed signal to a slave active control signal at selected one of the plurality of slave slices by the slice selection signal.
Dependencies are inferred from the claim text.