Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells

A method of forming an array of vertically stacked tiers of non-volatile cross point memory cells, comprising:

• forming multiple tiers that individually comprise a plurality of horizontally oriented word lines;
• forming a plurality of spaced sacrificial blocks adjacent the horizontal word lines;
• encapsulating the spaced sacrificial blocks within insulative material;
• etching openings into the insulative material to expose the spaced sacrificial blocks;
• etching the exposed spaced sacrificial blocks selectively relative to the insulative material and leaving void space there-behind;
• filling the void space with multi-resistive state material and forming programmable spaced blocks there-from;
• and
• forming a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells, individual of the local vertical bit line extensions being received laterally adjacent programmable spaced blocks received within multiple of the tiers.

A method of forming an array of vertically stacked tiers of non-volatile cross point memory cells, comprising:

• forming multiple tiers that individually comprise a plurality of horizontally oriented word lines;
• forming a plurality of spaced sacrificial blocks adjacent the horizontal word lines;
• encapsulating the spaced sacrificial blocks within insulative material;
• etching openings into the insulative material to expose the spaced sacrificial blocks;
• etching the exposed spaced sacrificial blocks selectively relative to the insulative material and leaving void spaces there-behind;
• lining the void spaces with multi-resistive state material;
• and
• depositing conductive material to within the lined void spaces and forming a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers of memory cells, individual of the local vertical bit line extensions comprising portions received laterally adjacent the lined void spaces received within multiple of the tiers.

A method of forming an array of vertically stacked tiers of non-volatile cross point memory cells, comprising:

• forming horizontally elongated trenches within insulative material;
• forming multiple tiers that individually comprise lateral recesses formed within the insulative material within the trenches;
• lining the trenches and lateral recesses with a first conductive material;
• filling the lined trenches and lined lateral recesses with a second conductive material which is different in composition from the first conductive material;
• etching the second conductive material within the trenches selectively relative to the first conductive material to leave second conductive material within the lined lateral recesses;
• after the etching of the second conductive material, etching the first conductive material selectively relative to the second conductive material to remove the first conductive material from being received over sidewalls of the trenches between the tiers to form a plurality of horizontally oriented word lines within individual of the tiers which comprise the first and second conductive materials;
• and
• forming a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers, individual of the local vertical bit line extensions being received laterally adjacent programmable spaced blocks received within multiple of the tiers, the programmable spaced blocks being received adjacent the horizontally oriented word lines.

A method of forming an array of vertically stacked tiers of non-volatile cross point memory cells, comprising:

• forming multiple tiers that individually comprise a plurality of horizontally oriented word lines, an elevationally outermost of the tiers comprising dummy horizontally oriented word lines that are non-functional within the array in a finished circuitry construction;
• etching openings into insulative material selectively relative to the horizontally oriented word lines using the dummy horizontally oriented word lines within the elevationally outermost tier as a hard mask to horizontally oriented word lines received elevationally inward thereof;
• and
• forming a plurality of horizontally oriented global bit lines having local vertical bit line extensions extending through multiple of the tiers, individual of the local vertical bit line extensions being received laterally adjacent programmable spaced blocks received within multiple of the tiers, the programmable spaced blocks being received adjacent the horizontally oriented word lines.