Systems and methods for improved timing recovery
AssigneeLSI Corporation
InventorViswanath Annampedu
Life of this patent
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Abstract
Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase.
Claims20
A timing recovery circuit, the circuit comprising:
- a first digital interpolation circuit operable to receive a data input and to provide a first interpolated output corresponding to a first phase;
- a second digital interpolation circuit operable to receive the data input and to provide a second interpolated output corresponding to a second phase;
- a phase selection circuit operable to select the first interpolated output and the second interpolated output, and to select the first phase for processing;
- and
- a sampling clock rotation circuit operable to move a sampling clock away from the first phase.
A method for timing recovery, the method comprising:
- receiving an analog signal;
- converting the analog signal to a series of digital samples at a phase corresponding to a sample clock;
- interpolating a sample from the series of digital samples to yield a first interpolated value corresponding to a first phase and a second interpolated value corresponding to a second phase;
- selecting one of the first phase or the second phase based upon the first interpolated value and the second interpolated value to yield a selected phase;
- and
- modifying the sample clock based upon the selected phase.
A storage device, the storage device comprising:
- a storage medium operable to store information;
- a read/write head assembly disposed in relation to the storage medium, wherein the read/write head assembly is operable to sense the information and to provide an analog signal corresponding to the information;
- and
- a read channel circuit comprising:
- an analog to digital converter circuit operable to convert a derivative of the analog signal into a series of digital samples at a phase corresponding to a sampling clock;
- a first digital interpolation circuit operable to receive a sample from the series of digital samples and to provide a first interpolated output corresponding to a first phase;
- a second digital interpolation circuit operable to receive the sample from the series of digital samples and to provide a second interpolated output corresponding to a second phase;
- a phase selection circuit operable to select the first phase for processing based at least in part on a comparison of the first interpolated value and the second interpolated value;
- and
- a sampling clock rotation circuit operable to move the sampling clock away from the first phase.
Dependencies are inferred from the claim text.