Gate driving circuit having a shift register stage capable of pulling down gate signals of a plurality of shift register stages

A gate driving circuit for providing a plurality of gate signals to drive a pixel array having a plurality of gate lines, the gate driving circuit comprising:

• a first shift register module comprising a plurality of odd shift register stages, each of the odd shift register stages providing a corresponding odd gate line of the gate lines with a corresponding gate signal of the gate signals according to a first clock and a second clock having a phase opposite to the first clock, the odd shift register stage being further employed to pull down at least one gate signal delivered by at least one even gate line of the gate lines or at least one odd gate line different from the corresponding odd gate line;
• and
• a second shift register module comprising a plurality of even shift register stages, each of the even shift register stages providing a corresponding even gate line of the gate lines with a corresponding gate signal of the gate signals according to a third clock and a fourth clock having a phase opposite to the third clock, the even shift register stage being further employed to pull down at least one gate signal delivered by at least one odd gate line of the gate lines or at least one even gate line different from the corresponding even gate line;
• wherein an (N+1)th shift register stage of the even shift register stages comprises:
• a pull-up unit, electrically connected to an (N+1)th gate line of the gate lines, for pulling up an (N+1)th gate signal of the gate signals to a high level voltage according to a driving control voltage and the third clock, wherein the (N+1)th gate line is employed to deliver the (N+1)th gate signal;
• an input unit for receiving an (N−1)th gate signal generated by an (N−1)th shift register stage of the even shift register stages;
• an energy-store unit, electrically connected to the pull-up unit and the input unit, for providing the driving control voltage to the pull-up unit through performing a charging process based on the (N−1)th gate signal;
• a first discharging unit, electrically connected to the energy-store unit, for pulling down the driving control voltage to a low power voltage according to a control signal, the first discharging unit comprising a transistor, the transistor comprising:
• a first end electrically connected to the energy-store unit;
• a gate end for receiving the control signal;
• and
• a second end for receiving the low power voltage;
• a second discharging unit, electrically connected to the energy-store unit, for pulling down the driving control voltage to the low power voltage according to an (N+3)th gate signal generated by an (N+3)th shift register stage of the even shift register stages;
• a pull-down module for pulling down the (N+1)th gate signal to the low power voltage according to the control signal and the fourth clock, the pull-down module being further employed to pull down the at least one gate signal delivered by the at least one odd gate line or the at least one even gate line different from the (N+1)th gate line;
• and
• a control unit, electrically connected to the energy-store unit, the gate end of the first discharging unit and the pull-down module, for generating the control signal according to the driving control voltage and the third clock;
• wherein N is a positive odd integer.

A gate driving circuit for providing a plurality of gate signals to drive a pixel array having a plurality of gate lines, the gate driving circuit comprising:

• a first shift register module comprising a plurality of odd shift register stages, each of the odd shift register stages providing a corresponding odd gate line of the gate lines with a corresponding gate signal of the gate signals according to a first clock and a second clock having a phase opposite to the first clock, the odd shift register stage being further employed to pull down at least one gate signal delivered by at least one even gate line of the gate lines or at least one odd gate line different from the corresponding odd gate line;
• and
• a second shift register module comprising a plurality of even shift register stages, each of the even shift register stages providing a corresponding even gate line of the gate lines with a corresponding gate signal of the gate signals according to a third clock and a fourth clock having a phase opposite to the third clock, the even shift register stage being further employed to pull down at least one gate signal delivered by at least one odd gate line of the gate lines or at least one even gate line different from the corresponding even gate line;
• wherein the second shift register module further comprises a preliminary shift register stage, the preliminary shift register stage being employed to pull down a corresponding gate signal delivered by a first or second gate line of the gate lines.