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US 8,411,016 B2Granted
Scanning drive circuit and display device including the same
AssigneeSony Corporation
InventorsTakao Tanikame, Seiichiro Jinta
Life of this patent
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Abstract
A scan driving circuit and a display device, the display device including display elements two-dimensionally disposed in a matrix; scanning lines, initialization control lines, and display control lines extending in a first direction; and data lines extending in a second direction different from the first direction. The scan driving circuit includes a shift register portion and a logic circuit portion, and generates scan signals and initialization signals, both based on two or more enable signals, and control signals. The scan driving circuit is configured such that changing the width of a start pulse (and thereby the ratio of a light emitting period to a non-light emitting period) does not affect the scan signals or the initialization signals.
Claims9
A display device, comprising:
- (1) display elements two-dimensionally disposed in a matrix;
- (2) M scanning lines, initialization control lines, and display control lines extending in a first direction, where M is an integer corresponding to the number of rows or columns of display elements;
- (3) data lines extending in a second direction different from the first direction;
- and
- (4) a scanning drive circuit;
- the scanning drive circuit including:
- (A) a shift register portion including P shift registers SRi, the shift register portion being configured to successively shift a start pulse inputted thereto, and to thereby output a plurality of register output signals STi from the shift registers SRi, respectively, where P is an integer greater than 2 and i=1, 2, . . . , P, and
- (B) a logical circuit portion including a plurality of logical circuits L(i,j), the logical circuit portion being configured to operate based on the register output signals STi outputted from the shift register portion, and Q kinds of enable signals, where Q is an integer greater than or equal to 2, and j=1, 2, . . . , Q,
- wherein:
- each of the logical circuits L(i,j) corresponds to one of the shift registers SRi,
- each of the logical circuits L(i=n,j) outputs a signal SCLk, where k=1, 2, . . . , M, based on inputs comprising:
- (a) a register input signal STi=n that is output by the shift register SRi=n that corresponds to the logical circuits L(i=n,j) and that is received as an input by the shift register SRi=n+1 that corresponds to the respective logical circuit L(i=n+1,j),
- (b) the register output signal STi=n+1 that is output from the shift register SRi=n+1 that corresponds to the respective logical circuit L(i=n+1,j), and
- (c) at least one enable signal,
- a scan signal is supplied to a given display element through an m-th scanning line, the scan signal corresponding to the signal SCLk=m output by one of the logic circuits L(i,j), where m=1, 2, . . . , M,
- a control signal Cm is supplied to the given display element through an m-th display control line, the control signal Cm corresponding to a register output signal STi that is also input into one of the logic circuits L(i,j), and
- a scan signal corresponding to the signal SCLk=m−1 output from one of the logic circuits L(i,j) and supplied to the (m−1)-th scanning line is also supplied as an initialization signal AZm to the given display element through an m-th initialization control line.
14 more elements
A scanning drive circuit, comprising:
- (A) a shift register portion including P shift registers SRi, the shift register portion being configured to successively shift a start pulse inputted thereto, and to thereby output a plurality of register output signals STi from the shift registers SRi, respectively, where P is an integer greater than 2 and i=1, 2, . . . , P, and
- (B) a logical circuit portion including a plurality of logical circuits L(i,j), the logical circuit portion being configured to operate based on the register output signals STi outputted from the shift register portion, and Q kinds of enable signals, where Q is an integer greater than or equal to 2, and j=1, 2, . . . , Q,
- wherein:
- each of the logical circuits L(i,j) corresponds to one of the shift registers SRi,
- each of the logical circuits L(i=n,j) outputs a signal SCLk, where k=1, 2, . . . , M, based on inputs comprising:
- (a) a register input signal STi=n that is output by the shift register SRi=n that corresponds to the logical circuits L(i=n,j) and that is received as an input by the shift register SRi=n+1 that corresponds to the respective logical circuit L(i=n+1,j),
- (b) the register output signal STi=n+1 that is output from the shift register SRi=n+1 that corresponds to the respective logical circuit L(i=n+1,j), and
- (c) at least one enable signal,
- a scan signal is supplied to a given display element through an m-th scanning line, the scan signal corresponding to the signal SCLk=m output one of the logic circuits L(i,j), where m=1, 2, . . . M,
- a control signal Cm is supplied to the given display element through an m-th display control line, the control signal Cm corresponding to a register output signal STi that is also input into one of the logic circuits L(i,j), and
- a scan signal corresponding to the signal SCLk=m−1 output from one of the logic circuits L(i,j) and supplied to the (m−1)-th scanning line is also supplied as an initialization signal AZm to the given display element through an m-th initialization control line.
8 more elements
Dependencies are inferred from the claim text.