Signal processing circuit and method

A signal processing method of a signal processing circuit including more than two digital signal processing means configured to perform processing in parallel wherein the data equivalent to one field of a picture signal to be input is written in field memory, and simultaneously read said data equivalent to one field from said field memory twice at double speed, thereby converting the frequency of said picture signal into double speed to output to a display unit made up of a collective entity of pixels, said method comprising the steps of:

• performing a selection control of one of a plurality of systems of picture signals which are input based on a mirror reversed setting, a master/slave setting associated with the plurality of digital signal processing means, and a display position setting, and performing a read position control of the picture temporarily stored in line memory included in said plurality of digital signal processing means, the display position setting indicating a number of dots shifted from a default position, wherein the mirror reversed setting, master/slave setting and display position setting are stored in a register located in each of the digital signal processing means, and wherein the display position setting includes a default setting, a default +1 setting in which each of the data is shifted and written onto a subsequent dot in relation to the default setting, and a default +2 setting in which the data is shifted and written onto a subsequent dot in relation to the default +1 setting;
• selecting one of said plurality of systems of picture signals based on said selection control and outputting the selected picture signals to double-speed converting means;
• writing the data equivalent to one field of the selected picture signal in said field memory, and simultaneously reading said data equivalent to one field from said field memory twice at double speed, thereby converting the frequency of said picture signal into double speed;
• implementing a serial-to-parallel conversion of the read data;
• reading out the picture signal converted into double speed, and temporarily stored in said line memory based on said read position control;
• and
• subjecting the read picture signal to predetermined correction processing,
• outputting one data of two data of the subjecting step to an external driver, wherein each digital signal processing means receives both odd data and even data of a picture.

A signal processing circuit configured to process a picture signal to output to a display unit made up of a collective entity of pixels, comprising:

• more than two digital signal processing units which operate in parallel each including
• a selecting unit configured to select one of a plurality of systems of picture signals which are input based on a mirror reversed setting, a master/slave setting associated with the plurality of digital signal processing means, and a display position setting, and output the selected picture signals to a double-speed converting unit, the display position setting indicating a number of dots shifted from a default position, wherein the mirror reversed setting, master/slave setting and display position setting are stored in a register located in each of the digital signal processing means, and wherein the display position setting includes a default setting, a default +1 setting in which each of the data is shifted and written onto a subsequent dot in relation to the default setting, and a default +2 setting in which the data is shifted and written onto a subsequent dot in relation to the default +1 setting,
• the double-speed converting unit configured to write the data equivalent to one field of the picture signal selected by said selecting unit in field memory, and simultaneously read said data equivalent to one field from said field memory twice at double speed, thereby converting the frequency of said picture signal into double speed,
• wherein the double-speed converting means further implements a serial-to-parallel conversion of the read data;
• a reading unit configured to read out the picture signal converted into double speed by said double-speed converting unit, and temporarily stored in line memory, and
• a correction processing unit configured to subject the picture signal read out by said reading unit to predetermined correction processing;
• and
• a switch unit configured to output one data of two data that are subjected to the correction processing unit to an external driver,
• wherein each digital signal processing unit receives both odd data and even data of a picture;
• and
• a control unit configured to perform a selection control of said plurality of systems of picture signals using said selecting unit, and to perform a read position control of a picture signal from said line memory using said reading unit.

A signal processing method of a signal processing circuit including more than two digital signal processing units configured to perform processing in parallel wherein the data equivalent to one field of a picture signal to be input is written in field memory, and simultaneously read said data equivalent to one field from said field memory twice at double speed, thereby converting the frequency of said picture signal into double speed to output to a display unit made up of a collective entity of pixels, said method comprising the steps of:

• performing a selection control of one of a plurality of systems of picture signals which are input based on a mirror reversed setting, a master/slave setting associated with the plurality of digital signal processing units, and a display position setting, and performing a read position control of the picture temporarily stored in line memory included in said plurality of digital signal processing units, wherein the mirror reversed setting, master/slave setting and display position setting are stored in a register located in each of the digital signal processing means, and wherein the display position setting includes a default setting, a default +1 setting in which each of the data is shifted and written onto a subsequent dot in relation to the default setting, and a default +2 setting in which the data is shifted and written onto a subsequent dot in relation to the default +1 setting;
• selecting one of said plurality of systems of picture signals based on said selection control and outputting the selected picture signals to a double-speed converting unit;
• writing the data equivalent to one field of the selected picture signal in said field memory, and simultaneously reading said data equivalent to one field from said field memory twice at double speed, thereby converting the frequency of said picture signal into double speed;
• implementing a serial-to-parallel conversion of the read data;
• reading out the picture signal converted into double speed, and temporarily stored in said line memory based on said read position control;
• and
• subjecting the read picture signal to predetermined correction processing,
• outputting one data of two data of the subjecting step to an external driver,
• wherein each digital signal processing unit receives both odd data and even data of a picture.