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US 8,410,997 B2Granted
Driving circuit, driving method and plasma display panel having scan line groups receiving reset signals at different times
AssigneeSamsung SDI Co., Ltd.
InventorSang-gu Lee
Life of this patent
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Abstract
A PDP driving circuit is disclosed. The circuit includes a scan driver divided into at least more than two groups, a logic controller generating scan driver control reference signals, which are used to generate scan driving signals of the scan driver, and a buffer block giving different delay times to the scan driver control reference signals, to apply them to the scan driver groups, respectively.
Claims21
A plasma display panel driving circuit, comprising:
- a logic controller configured to generate a plurality of scan driver reset control reference signals;
- a buffer block configured to receive the scan driver reset control reference signals and to generate at least three reset control signals based on the scan driver reset control reference signals, wherein each of the reset control signals has a selected one of at least three different selectable delay times;
- and
- a scan driver configured to drive a plurality of scan lines with reset driving signals, wherein the scan lines are divided into at least three groups, wherein the reset driving signals for each of the groups is based on one of the three reset control signals, and wherein the reset driving signals of each of the groups comprises:
- a voltage ramp starting at a start voltage and ending at an end voltage, wherein the start and end voltages for each of the groups is substantially the same, and wherein the voltage ramp of each of the groups occurs at substantially the same time,
- a voltage transition to the start voltage, which occurs at a time based on the selected delay times of the reset control signals, and
- a voltage transition from the end voltage, which occurs at a time based on the selected delay times of the reset control signals.
4 more elements
A method of driving a plasma display panel comprising a logic controller and a plurality of scan drivers, the method comprising:
- generating a plurality of scan driver reset control reference signals in a logic controller, the scan driver reset control reference signals being digital signals;
- transferring the scan driver reset control reference signals to the scan drivers, each of the transferred signals having a selected one of at least three different selectable delay times in at least one transition time point;
- generating a plurality of scan driving signals according to the transferred scan driver reset control reference signals, each of the scan signals having one of at least three different delay times according to the selectable delay times of the transferred scan driver reset control reference signals, wherein the scan signals comprises:
- a voltage ramp starting at a start voltage and ending at an end voltage, wherein the start and end voltages of the scan signals for each of the selectable delay times is substantially the same, and wherein the voltage ramp of the scan signals for each of the selectable delay times occurs at substantially the same time,
- a voltage transition to the start voltage, which occurs at a time based on the selected delay times of the reset control reference signals, and
- a voltage transition from the end voltage, which occurs at a time based on the selected delay times of the reset control reference signals;
- and
- driving the plasma display panel according to the scan driving signals.
5 more elements
A plasma display device comprising:
- a plasma display panel including a plurality of discharge electrodes, each of the discharge electrodes belonging to one of more than two groups;
- and
- a driving circuit module configured to separately drive each of the groups of discharge electrodes with driving signals each including a reset waveform, an address waveform, and a sustain waveform, wherein the driving circuit module comprises a buffer block configured to generate a reset control signal for each of the groups wherein each of the reset control signals has a selected one of at least three different selectable delay times;
- wherein the reset waveform of each of the groups comprises:
- a voltage ramp starting at a start voltage and ending at an end voltage, wherein the start and end voltages for each of the groups is substantially the same, and wherein the voltage ramp of each of the groups occurs at substantially the same time,
- a voltage transition to the start voltage, which occurs at a time based on the selected delay times of the reset control signals, and
- a voltage transition from the end voltage, which occurs at a time based on the selected delay times of the reset control signals.
4 more elements
Dependencies are inferred from the claim text.