US 8,410,961 B2Granted

Semiconductor integrated circuit

AssigneeRenesas Electronics Corporation

InventorMasaru Iwabuchi

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Abstract

In combining an analog terminal of an A/D converter with a digital terminal, the effect of the noise from the digital terminal is reduced. A semiconductor integrated circuit includes a high-speed external terminal, a low-speed external terminal, a high-speed analog switch, a low-speed analog switch, and an A/D converter. The high-speed external terminal is coupled to an input of the A/D converter via the high-speed analog switch, and the low-speed external terminal is coupled to the input of the A/D converter via the low-speed analog switch. A plurality of inputs of a plurality of low-speed digital input buffer circuits and a plurality of outputs of a plurality of low-speed digital output buffer circuits are coupled to a plurality of low-speed external terminals. The output of any digital output buffer circuit is not coupled to a plurality of high-speed external terminals, but a plurality of inputs of a plurality of high-speed digital input buffer circuits is coupled to a plurality of high-speed external terminals. Between a plurality of low-speed external terminals and the input of the A/D converter, a low-speed separating resistor with a high resistance value is coupled, respectively.

Claims20

Dependent claims

A semiconductor integrated circuit comprising a plurality of high-speed external terminals, a plurality of low-speed external terminals, a plurality of high-speed analog switches, a plurality of low-speed analog switches, and an A/D converter, wherein

each terminal of the high-speed external terminals is connectable to an input terminal of the A/D converter via each switch of the high-speed analog switches, wherein
each terminal of the low-speed external terminals is connectable to the input terminal of the A/D converter via each switch of the low-speed analog switches, wherein
a plurality of input terminals of a plurality of low-speed digital input buffer circuits and a plurality of output terminals of a plurality of low-speed digital output buffer circuits are coupled to the low-speed external terminals, respectively, wherein
a plurality of output terminals of any digital output buffer circuit is not coupled, but a plurality of input terminals of a plurality of high-speed digital input buffer circuits is coupled to the high-speed external terminals, and wherein
between each of the terminals of the low-speed external terminals and each of the switches of the low-speed analog switches, a low-speed separating resistor set to resistance value higher than a resistance value between each of the terminals of the high-speed external terminals and each of the switches of the high-speed analog switches is coupled.

2 more elements

Dependencies are inferred from the claim text.