Power switch circuit

A power switch circuit, comprising:

• a control circuit comprising first to fifth field effect transistors (FETs), a first sensing resistor, a second sensing resistor, and a voltage output terminal, wherein a gate of the first FET is connected to a signal pin of a power supply, a source of the first FET is grounded, a drain of the first FET is connected to a first power port of the power supply through a first resistor, connected to a gate of the second FET, and also connected to a gate of the third FET, sources of the second and third FETs are grounded, a drain of the second FET is connected to a power source through a second resistor and also connected to a gate of the fourth FET, a source of the fourth FET is connected to a second power port of the power supply and also grounded through a first capacitor, a drain of the fourth FET is connected to a first end of the first sensing resistor, a second end of the first sensing resistor is connected to the voltage output terminal, a drain of the third FET is connected to the first power port of the power supply through a third resistor and also connected to a gate of the fifth FET, a drain of the fifth FET is connected to the first power port of the power supply and also grounded through a second capacitor, a source of the fifth FET is connected to a first end of the second sensing resistor, a second end of the second sensing resistor is connected to the second end of the first sensing resistor and the voltage output terminal;
• a first detecting circuit comprising two input terminals connected to the first and the second ends of the first sensing resistor and an output terminal connected to the gate of the fourth FET, wherein the first detecting circuit controls the fourth FET to be turned on or turned off according to voltages of the first and second ends of the first sensing resistor;
• and
• a second detecting circuit comprising two input terminals connected to the first and second ends of the second sensing resistor and an output terminal connected to the gate of the fifth FET, wherein the second detecting circuit controls the fifth FET to be turned on or turned off according to voltages of the first and second ends of the second sensing resistor.